linux/drivers/gpu/drm/amd/include, branch v5.9Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v5.92020-09-18T03:05:57Zdrm/amdgpu: add VCN 3.0 AV1 registers2020-09-18T03:05:57ZAlex Deucheralexander.deucher@amd.com2020-05-01T20:45:09Zurn:sha1:1b51916b9734acd609c4f552e582cdc59ac254d6
This adds the AV1 registers.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add the GC 10.3 VRS registers2020-09-18T03:05:42ZAlex Deucheralexander.deucher@amd.com2020-05-01T20:42:56Zurn:sha1:5d5b71e8a0f2f5649991d651d005181dc087981c
Add the VRS registers.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Read VBIOS Golden Settings Tbl2020-08-06T20:47:13ZIgor KravchenkoIgor.Kravchenko@amd.com2020-07-20T00:45:28Zurn:sha1:098214999c8f8eea8dffddb61be5742fac2c829e
[Why]
For ver.4.4 and higher VBIOS contains default setting table.
{How]
Read Golden Settings Table from VBIOS, apply Aux tuning parameters.
Signed-off-by: Igor Kravchenko <Igor.Kravchenko@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/atomfirmware: update to latest integratedinfotable2020-07-02T16:02:57ZAlex Deucheralexander.deucher@amd.com2020-06-25T21:46:46Zurn:sha1:2fde24e4dc8adc73ba69c5eea347822d5b8a2423
Used for renoir.
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm amdgpu: SI UVD registers2020-07-01T05:59:24ZSonny Jiangsonny.jiang@amd.com2020-06-10T20:02:21Zurn:sha1:2282b4186dee80c89906d0ee10295393582c3afd
Add SI UVD registers files.
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)2020-07-01T05:59:22ZTom St Denistom.stdenis@amd.com2020-06-16T12:47:04Zurn:sha1:614c56111cc73f0a828634dcb2eecd2035c2104b
Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10. This patch fixes the offset relative
to the GC block on gfx10.
(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers2020-07-01T05:59:21ZTom St Denistom.stdenis@amd.com2020-06-15T16:17:46Zurn:sha1:e3569fab49886123c81f18d675fb1719d73cf27d
Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits2020-07-01T05:59:19ZTom St Denistom.stdenis@amd.com2020-06-11T11:54:13Zurn:sha1:8d7fb7a10a825bd2e2c0fde7979cd8774c332bea
Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.
Requested for UMR debugging.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2)2020-07-01T05:59:19ZTom St Denistom.stdenis@amd.com2020-06-09T11:49:59Zurn:sha1:055e23e3d9ea1d680977f8e34f9678c17cb3cfc1
Requested for UMR support.
(v2): Also add reg/bits for gfx9 headers
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: and smc dpm info struct for sienna_cichlid2020-07-01T05:59:13ZLikun GaoLikun.Gao@amd.com2020-04-17T18:03:19Zurn:sha1:44e7139b45a236fe0337b66fbfbdabce3a95dae0
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>