Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ https://git.shady.money/linux/atom?h=v6.0 2022-09-27T21:54:12Z 2022-09-27T21:54:12Z Graham Sider Graham.Sider@amd.com 2022-09-19T17:57:14Z urn:sha1:91ef6cfd30bf75763f41e7a4bc119883fe190606 Update mes_v11_api_def.h add_queue API with is_aql_queue parameter. Also re-use gds_size for the queue size (unused for KFD). MES requires the queue size in order to compute the actual wptr offset within the queue RB since it increases monotonically for AQL queues. v2: Make is_aql_queue assign clearer Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-08-30T20:56:21Z Graham Sider Graham.Sider@amd.com 2022-08-15T17:28:19Z urn:sha1:47e04eed84bb07cc5b54462752a4bc7286ab8197 New GFX11 MES FW adds the trap_en bit. For now hardcode to 1 (traps enabled). Signed-off-by: Graham Sider <Graham.Sider@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-08-25T17:52:48Z Tim Huang tim.huang@amd.com 2022-08-15T05:03:49Z urn:sha1:ad3b0b99113783f697579c7b09285916019865ea Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro definitions for AMD_CG_SUPPORT_BIF_LS. Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-29T19:24:38Z Xiaojian Du Xiaojian.Du@amd.com 2022-07-28T05:23:38Z urn:sha1:492af34c9f67ef864319d0db930c8518a04b1937 This patch will add header files for MP 13.0.4. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-28T20:19:59Z Chengming Gui Jack.Gui@amd.com 2022-06-20T07:52:29Z urn:sha1:7c8e4a257246399c4f1ff43a06fc53ec53423754 Add three additional page fault settings. V2: move reg offset definition to header file. (Alex) V3: add all shift/mask definitions of used reg. (Hawking) Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-25T13:31:05Z Slark Xiao slark_xiao@163.com 2022-07-21T06:09:46Z urn:sha1:9dd4545f65679042273a93054ec3bb665ecf7366 Replace 'the the' with 'the' in the comment. Signed-off-by: Slark Xiao <slark_xiao@163.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-25T13:31:03Z Leo Li sunpeng.li@amd.com 2022-07-06T18:56:28Z urn:sha1:8813381a62e1f1703f8fbeccc5fa4fcc988be882 [Why & How] It's useful to disable MPO when debugging or testing. Therefore, add a dcdebugmask option to disable MPO. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-18T20:37:38Z YiPeng Chai YiPeng.Chai@amd.com 2022-07-04T09:16:38Z urn:sha1:75510fac07cdde23c9217c8299b6cd64c689fb2b Add umc v8_10_0 register offset and shift masks header files Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-14T00:57:04Z Roman Li roman.li@amd.com 2022-06-28T19:06:23Z urn:sha1:8955ff11f56e1596e9f80ff6fa8c48e53047654c Register headers for the following IPs: - DCN 3.1.4 - DPCS 3.1.4 v2:(squash) clean up (Alex) Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-07-13T15:25:18Z Alex Deucher alexander.deucher@amd.com 2022-07-12T13:22:23Z urn:sha1:0a94608f0f7de9b1135ffea3546afe68eafef57f Drop execute. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2085 Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>