linux/drivers/gpu/drm/amd/include, branch v6.16Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
https://git.shady.money/linux/atom?h=v6.162025-06-03T19:32:50Zdrm/amdgpu: Add userq fence support to SDMAv7.02025-06-03T19:32:50ZArunpravin Paneer SelvamArunpravin.PaneerSelvam@amd.com2025-05-27T13:43:20Zurn:sha1:e34bcf1594b59f9f63c084bf0646b19edf581adc
- Add userq fence support to SDMAv7.0.
- GFX12's user fence irq src id differs from GFX11's,
hence we need create a new irq srcid header file for GFX12.
User fence irq src id information-
GFX11 and SDMA6.0 - 0x43
GFX12 and SDMA7.0 - 0x46
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add userq fence support to SDMAv6.02025-05-29T14:56:58ZArunpravin Paneer SelvamArunpravin.PaneerSelvam@amd.com2024-12-30T16:54:53Zurn:sha1:5ae9de5867dbf23e53d244dfd62216bec95234a8
Add userq fence support to SDMAv6.0
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Reuse Subvp debug option for FAMS2025-05-29T14:54:56ZAurabindo Pillaiaurabindo.pillai@amd.com2025-05-22T14:34:50Zurn:sha1:040585df957d45ebec0297bad525f39471229987
FAMS is the successor to SubVP starting with DCN4x. Reuse the same
debug option to disable FAMS for debugging purposes.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add some missing register headers for DCN4012025-05-28T20:01:50ZAurabindo Pillaiaurabindo.pillai@amd.com2025-05-21T19:59:56Zurn:sha1:d78eb800f8f5169db89a28380631aefc224a76bb
Add some HDCP related register headers for future use.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add jpeg poison status reg2025-05-22T16:02:49ZMangesh GadreMangesh.Gadre@amd.com2025-05-14T05:17:02Zurn:sha1:8d74ce4e5524b39e991bfa025f1382e54c5f710a
added registers to enable jpeg ras
Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add a new dcdebugmask to allow skip detection LT2025-05-22T16:02:40ZWayne LinWayne.Lin@amd.com2025-05-20T01:34:42Zurn:sha1:076873e5b360ccd91687e23c6ca0042a0356b9eb
Under specific embedded scenarios, we might still use DP interface
rather than eDP interface. Under such case, detection link training
is unnecessary.
Add a new dcdebugmask value that can be used to skip the detection LT
Reviewed-by: Tom Chung <chiahsuan.chung@amd.com>
Link: https://lore.kernel.org/amd-gfx/20250521063934.2111323-1-Wayne.Lin@amd.com/
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add vcn poison status reg2025-05-22T16:02:10ZMangesh GadreMangesh.Gadre@amd.com2025-05-14T04:31:36Zurn:sha1:f55fcf15a9c585d0a3f294307f1499d3759459c6
added register to enable vcn ras
Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fixing typo in macro name2025-05-22T16:01:57ZJihed Chaibijihed.chaibi.dev@gmail.com2025-05-17T03:06:09Zurn:sha1:ae6f4ab96be19395b8977f65670ae60d01096a83
"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS
PS: checkpatch.pl is complaining about the presence of a space at the
start of drivers/gpu/drm/amd/include/atomfirmware.h line: 1716
This is propably because this file uses (two) spaces and not tabs.
Signed-off-by: Jihed Chaibi <jihed.chaibi.dev@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pm: Add support to query partition metrics2025-05-22T16:01:33ZLijo Lazarlijo.lazar@amd.com2025-05-05T11:23:29Zurn:sha1:54a01f775194a8b5acc6bd735aa0d092469dcff7
Add interfaces to query compute partition related metrics data.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vcn v5_0_0 ip headers2025-05-13T13:31:51ZfanhuangFangSheng.Huang@amd.com2025-05-06T06:49:18Zurn:sha1:80f66ca7a45889d2a8eecf61c3069117b3279b3f
Add vcn v5_0_0 register offset and shift masks
header files
Only include the registers required for MMSCH
initialization
Signed-off-by: fanhuang <FangSheng.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>