<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include, branch v6.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-06-24T14:02:44Z</updated>
<entry>
<title>drm/amd/pm: Add support to set min ISP clocks</title>
<updated>2025-06-24T14:02:44Z</updated>
<author>
<name>Pratap Nirujogi</name>
<email>pratap.nirujogi@amd.com</email>
</author>
<published>2025-06-16T18:16:43Z</published>
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<id>urn:sha1:9bed716f8722999a2b15a2e5df4dfca48e4c06c9</id>
<content type='text'>
Add support to set ISP clocks for SMU v14.0.0. ISP driver
uses amdgpu_dpm_set_soft_freq_range() API to set clocks via
SMU interface than communicating with PMFW directly.

amdgpu_dpm_set_soft_freq_range() is updated to take in any
pp_clock_type than limiting to support only PP_SCLK to allow
ISP and other driver modules to set the min/max clocks. Any
clock specific restrictions are expected to be taken care in
SOC specific SMU implementations instead of generic amdgpu_dpm
and amdgpu_smu interfaces.

Reviewed-by: Xiaojian Du &lt;xiaojian.du@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Pratap Nirujogi &lt;pratap.nirujogi@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Add missing kdoc for amd_ip_funcs `complete` callback</title>
<updated>2025-06-24T14:00:07Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2025-06-20T04:14:20Z</published>
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<id>urn:sha1:bb233caa85d5f51916244574f735b22af46c89f0</id>
<content type='text'>
The `complete` callback should be described in kernel doc.

Reported-by: Stephen Rothwell &lt;sfr@canb.auug.org.au&gt;
Closes: https://lore.kernel.org/linux-next/20250619205931.41cf9332@canb.auug.org.au/
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://lore.kernel.org/r/20250620041420.3585005-1-superm1@kernel.org
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Add support for a complete pmops action</title>
<updated>2025-06-18T16:19:18Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2025-06-02T01:44:30Z</published>
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<id>urn:sha1:64c3e4a868f1ddde8eee2bb038a2ed0e8f06a247</id>
<content type='text'>
complete() callbacks are supposed to handle reversing anything
that occurred during prepare() callbacks.  They'll be called on every
power state transition, and will also be called if the sequence is
failed (such as an aborted suspend).

Add support for IP blocks to support this action.

Reviewed-by: Alex Hung &lt;alex.hung@amd.com&gt;
Link: https://lore.kernel.org/r/20250602014432.3538345-2-superm1@kernel.org
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add userq fence support to SDMAv7.0</title>
<updated>2025-06-03T19:32:50Z</updated>
<author>
<name>Arunpravin Paneer Selvam</name>
<email>Arunpravin.PaneerSelvam@amd.com</email>
</author>
<published>2025-05-27T13:43:20Z</published>
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<id>urn:sha1:e34bcf1594b59f9f63c084bf0646b19edf581adc</id>
<content type='text'>
- Add userq fence support to SDMAv7.0.
- GFX12's user fence irq src id differs from GFX11's,
  hence we need create a new irq srcid header file for GFX12.

  User fence irq src id information-
  GFX11 and SDMA6.0 - 0x43
  GFX12 and SDMA7.0 - 0x46

Signed-off-by: Arunpravin Paneer Selvam &lt;Arunpravin.PaneerSelvam@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add userq fence support to SDMAv6.0</title>
<updated>2025-05-29T14:56:58Z</updated>
<author>
<name>Arunpravin Paneer Selvam</name>
<email>Arunpravin.PaneerSelvam@amd.com</email>
</author>
<published>2024-12-30T16:54:53Z</published>
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<id>urn:sha1:5ae9de5867dbf23e53d244dfd62216bec95234a8</id>
<content type='text'>
Add userq fence support to SDMAv6.0

Signed-off-by: Arunpravin Paneer Selvam &lt;Arunpravin.PaneerSelvam@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Reuse Subvp debug option for FAMS</title>
<updated>2025-05-29T14:54:56Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2025-05-22T14:34:50Z</published>
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<id>urn:sha1:040585df957d45ebec0297bad525f39471229987</id>
<content type='text'>
FAMS is the successor to SubVP starting with DCN4x. Reuse the same
debug option to disable FAMS for debugging purposes.

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add some missing register headers for DCN401</title>
<updated>2025-05-28T20:01:50Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2025-05-21T19:59:56Z</published>
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<id>urn:sha1:d78eb800f8f5169db89a28380631aefc224a76bb</id>
<content type='text'>
Add some HDCP related register headers for future use.

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Reviewed-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add jpeg poison status reg</title>
<updated>2025-05-22T16:02:49Z</updated>
<author>
<name>Mangesh Gadre</name>
<email>Mangesh.Gadre@amd.com</email>
</author>
<published>2025-05-14T05:17:02Z</published>
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<id>urn:sha1:8d74ce4e5524b39e991bfa025f1382e54c5f710a</id>
<content type='text'>
added registers to enable jpeg ras

Signed-off-by: Mangesh Gadre &lt;Mangesh.Gadre@amd.com&gt;
Reviewed-by: Stanley.Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add a new dcdebugmask to allow skip detection LT</title>
<updated>2025-05-22T16:02:40Z</updated>
<author>
<name>Wayne Lin</name>
<email>Wayne.Lin@amd.com</email>
</author>
<published>2025-05-20T01:34:42Z</published>
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<id>urn:sha1:076873e5b360ccd91687e23c6ca0042a0356b9eb</id>
<content type='text'>
Under specific embedded scenarios, we might still use DP interface
rather than eDP interface. Under such case, detection link training
is unnecessary.

Add a new dcdebugmask value that can be used to skip the detection LT

Reviewed-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Link: https://lore.kernel.org/amd-gfx/20250521063934.2111323-1-Wayne.Lin@amd.com/
Signed-off-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add vcn poison status reg</title>
<updated>2025-05-22T16:02:10Z</updated>
<author>
<name>Mangesh Gadre</name>
<email>Mangesh.Gadre@amd.com</email>
</author>
<published>2025-05-14T04:31:36Z</published>
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<id>urn:sha1:f55fcf15a9c585d0a3f294307f1499d3759459c6</id>
<content type='text'>
added register to enable vcn ras

Signed-off-by: Mangesh Gadre &lt;Mangesh.Gadre@amd.com&gt;
Reviewed-by: Stanley.Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
