<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd/include, branch v6.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.3'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-02-16T03:26:22Z</updated>
<entry>
<title>drm/amd/display: disable SubVP + DRR to prevent underflow</title>
<updated>2023-02-16T03:26:22Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2023-02-15T17:51:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=80c6d6804f31451848a3956a70c2bcb1f07cfcb0'/>
<id>urn:sha1:80c6d6804f31451848a3956a70c2bcb1f07cfcb0</id>
<content type='text'>
[Why&amp;How]
Temporarily disable SubVP+DRR since Xorg has an architectural limitation
where freesync will not work in a multi monitor configuration. SubVP+DRR
requires that freesync be working.

Whether OS has variable refresh setting enabled or not, the state on
the crtc remains same unless an application requests VRR. Due to this,
there is no way to know whether freesync will actually work or not
while we are on the desktop from the kernel's perspective.

If userspace does not have a limitation with multi-display freesync (for
example wayland), then this feature can be enabled by adding a
dcfeaturemask option to amdgpu on the kernel cmdline like:

amdgpu.dcfeaturemask=0x200

Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10</title>
<updated>2023-02-14T20:47:15Z</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2023-02-10T05:04:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=230dd6bb61173acccdfbf855ba907286e850cd67'/>
<id>urn:sha1:230dd6bb61173acccdfbf855ba907286e850cd67</id>
<content type='text'>
implement mode2 reset on smu_v13_0_10

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: correct query xgmi3x16 pcs error status</title>
<updated>2023-01-17T21:11:52Z</updated>
<author>
<name>Stanley.Yang</name>
<email>Stanley.Yang@amd.com</email>
</author>
<published>2023-01-16T07:42:36Z</published>
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<id>urn:sha1:442d61af795c1441614064d8e6f2309223a8b342</id>
<content type='text'>
There is xgmi3x16 pcs error status for aldebaran, driver should
check xgmi3x16 pcs error status field instead of gopx16 pcs error
status field.

Signed-off-by: Stanley.Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add gfx ras poison consumption irq handling on gfx v11_0_3</title>
<updated>2023-01-17T21:11:51Z</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2023-01-05T06:53:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ae6f2db4d59e9f8c90cb3c2d2a954832898d0f2b'/>
<id>urn:sha1:ae6f2db4d59e9f8c90cb3c2d2a954832898d0f2b</id>
<content type='text'>
Add gfx ras poison consumption irq handling on gfx v11_0_3.

V2:
  Move ras poison consumption irq handling code of gfx
     v11_0_3 to gfx_v11_0_3.c.
V5:
  Create dedicated irq handler for RLC_GC_FED_INTERRUPT.

V6:
  Remove invalid function call.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers</title>
<updated>2023-01-17T21:11:50Z</updated>
<author>
<name>YiPeng Chai</name>
<email>YiPeng.Chai@amd.com</email>
</author>
<published>2023-01-05T06:52:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=79d949a2d688b09b1ff840a2366a8cfe1b7a2651'/>
<id>urn:sha1:79d949a2d688b09b1ff840a2366a8cfe1b7a2651</id>
<content type='text'>
V2:
   Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register
   offset and shift masks.

Signed-off-by: YiPeng Chai &lt;YiPeng.Chai@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add df v4_3 headers</title>
<updated>2022-12-15T17:19:22Z</updated>
<author>
<name>Candice Li</name>
<email>candice.li@amd.com</email>
</author>
<published>2022-09-19T06:44:40Z</published>
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<id>urn:sha1:6c03a3fc912f74fe2ff588b42d30f52bc9001ab8</id>
<content type='text'>
Add df v4_3 header files.

Signed-off-by: Candice Li &lt;candice.li@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: fulfill swsmu peak profiling mode shader/memory clock settings</title>
<updated>2022-12-15T17:18:40Z</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2022-12-05T04:02:35Z</published>
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<id>urn:sha1:975b4b1d90ccf83da252907108f4090fb61b816e</id>
<content type='text'>
Enable peak profiling mode shader/memory clocks reporting for swsmu
framework.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: update mes11 api def</title>
<updated>2022-12-01T16:49:32Z</updated>
<author>
<name>Jack Xiao</name>
<email>Jack.Xiao@amd.com</email>
</author>
<published>2022-11-29T03:12:08Z</published>
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<id>urn:sha1:1e7bbdba68baf6af7500dd636f18b6fcce58e945</id>
<content type='text'>
Update the api def of mes11.

Signed-off-by: Jack Xiao &lt;Jack.Xiao@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Tested-and-acked-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add missing license to some files</title>
<updated>2022-11-23T15:31:31Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-11-21T17:17:33Z</published>
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<id>urn:sha1:e93e075d340859af772214c267d27f09f9db3e51</id>
<content type='text'>
The driver is MIT, so add the licenses.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2265
Acked-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add register definition for VCN RAS initialization</title>
<updated>2022-11-23T15:31:31Z</updated>
<author>
<name>Tao Zhou</name>
<email>tao.zhou1@amd.com</email>
</author>
<published>2022-10-27T09:50:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=88733d68014f06d4aae8ef0673ee31602ef1f0a7'/>
<id>urn:sha1:88733d68014f06d4aae8ef0673ee31602ef1f0a7</id>
<content type='text'>
Prepare for enableing VCN RAS poison.

v2: move SHIFT and MASK definitions to related sh_mask.h file.

Signed-off-by: Tao Zhou &lt;tao.zhou1@amd.com&gt;
Signed-off-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
