<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd, branch v4.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-07-14T20:39:35Z</updated>
<entry>
<title>drm/amdgpu: fix power distribution issue for Polaris10 XT</title>
<updated>2016-07-14T20:39:35Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-07-11T05:33:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=eeade25ad029cb1f31f27f8e0ddc9bb9c22b5537'/>
<id>urn:sha1:eeade25ad029cb1f31f27f8e0ddc9bb9c22b5537</id>
<content type='text'>
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add a missing register to Polaris golden setting</title>
<updated>2016-07-14T20:39:30Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-07-07T01:56:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=795c2109c287123dfc3bc987d20daef32d77e4d1'/>
<id>urn:sha1:795c2109c287123dfc3bc987d20daef32d77e4d1</id>
<content type='text'>
Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation.</title>
<updated>2016-07-06T21:56:31Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-06-28T20:55:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ab6bad05c886cf0ef0c86bd1f665cdbe8e5e75e7'/>
<id>urn:sha1:ab6bad05c886cf0ef0c86bd1f665cdbe8e5e75e7</id>
<content type='text'>
As get the right evv voltage, update them to latest coefficients to
align with BB.

agd: squash in Slava's 32 bit build fix

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: fix bug that get wrong polaris evv voltage.</title>
<updated>2016-07-06T21:44:14Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-06-29T08:37:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e5eb37170b3cbbf948c6aeaccece818a59e76a6c'/>
<id>urn:sha1:e5eb37170b3cbbf948c6aeaccece818a59e76a6c</id>
<content type='text'>
value is 32 bits for polaris, not 16.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: incorrectly use of the function return value</title>
<updated>2016-07-06T21:43:59Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-07-05T05:11:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4b2427605e5325eafb5cfc2698f517db68e41075'/>
<id>urn:sha1:4b2427605e5325eafb5cfc2698f517db68e41075</id>
<content type='text'>
'0' means true.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Michel Dänzer &lt;michel.daenzer@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/powerplay: fix incorrect voltage table value for tonga</title>
<updated>2016-07-06T20:16:43Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2016-07-06T01:32:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1dfefee8939b07dd65a35bb78f6a06df85578301'/>
<id>urn:sha1:1dfefee8939b07dd65a35bb78f6a06df85578301</id>
<content type='text'>
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amd/powerplay: fix incorrect voltage table value for polaris10</title>
<updated>2016-07-06T20:16:09Z</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2016-07-06T01:31:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=095d28c62f9a05edc186e1b2b02bc44585402bdd'/>
<id>urn:sha1:095d28c62f9a05edc186e1b2b02bc44585402bdd</id>
<content type='text'>
Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: workaround for UVD clock issue</title>
<updated>2016-06-29T16:12:26Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-06-28T08:22:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a7f14a184e0e8e94becfc3f9608f6b0f9c339572'/>
<id>urn:sha1:a7f14a184e0e8e94becfc3f9608f6b0f9c339572</id>
<content type='text'>
workaround issue that when uvd dpm disabled,
uvd clock remain high on polaris10. Manually turn
off the clocks.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add ACLK_CNTL setting for polaris10</title>
<updated>2016-06-29T16:10:31Z</updated>
<author>
<name>Ken Wang</name>
<email>Qingqing.Wang@amd.com</email>
</author>
<published>2016-06-28T05:28:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d9d533c1483c4daf76e7e720c35896a430563ff8'/>
<id>urn:sha1:d9d533c1483c4daf76e7e720c35896a430563ff8</id>
<content type='text'>
This is a temporary workaround for early boards.

Signed-off-by: Ken Wang &lt;Qingqing.Wang@amd.com&gt;
Reviewed-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: fix issue uvd dpm can't enabled on Polaris11.</title>
<updated>2016-06-29T16:10:02Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2016-06-27T09:30:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0636e0d666e0238fa22348172c20a49f42a94395'/>
<id>urn:sha1:0636e0d666e0238fa22348172c20a49f42a94395</id>
<content type='text'>
1. Populate correct value of VDDCI voltage for SMC SAMU, VCE,
   and UVD levels depending on whether VDDCi control is SVI2 or GPIO.
2. Populate SMC ACPI minimum voltage using VBIOS boot SCLK and MCLK

When static voltage is configured as VDDCI, driver still tries to program
a voltage for MM minVoltage using VDDC-VDDCI delta requirement.
minVoltage should be set as boot up voltage.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
