<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd, branch v5.1</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.1</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.1'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-04-15T04:45:43Z</updated>
<entry>
<title>drm/amd/display: If one stream full updates, full update all planes</title>
<updated>2019-04-15T04:45:43Z</updated>
<author>
<name>David Francis</name>
<email>David.Francis@amd.com</email>
</author>
<published>2019-03-29T17:23:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c238bfe0be9ef7420f7669a69e27c8c8f4d8a568'/>
<id>urn:sha1:c238bfe0be9ef7420f7669a69e27c8c8f4d8a568</id>
<content type='text'>
[Why]
On some compositors, with two monitors attached, VT terminal
switch can cause a graphical issue by the following means:

There are two streams, one for each monitor. Each stream has one
plane

current state:
	M1:S1-&gt;P1
	M2:S2-&gt;P2

The user calls for a terminal switch and a commit is made to
change both planes to linear swizzle mode. In atomic check,
a new dc_state is constructed with new planes on each stream

new state:
	M1:S1-&gt;P3
	M2:S2-&gt;P4

In commit tail, each stream is committed, one at a time. The first
stream (S1) updates properly, triggerring a full update and replacing
the state

current state:
	M1:S1-&gt;P3
	M2:S2-&gt;P4

The update for S2 comes in, but dc detects that there is no difference
between the stream and plane in the new and current states, and so
triggers a fast update. The fast update does not program swizzle,
so the second monitor is corrupted

[How]
Add a flag to dc_plane_state that forces full updates

When a stream undergoes a full update, set this flag on all changed
planes, then clear it on the current stream

Subsequent streams will get full updates as a result

Signed-off-by: David Francis &lt;David.Francis@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet Lakha@amd.com&gt;
Acked-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gmc9: fix VM_L2_CNTL3 programming</title>
<updated>2019-04-12T16:24:16Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-04-11T19:54:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1925e7d3d4677e681cc2e878c2bdbeaee988c8e2'/>
<id>urn:sha1:1925e7d3d4677e681cc2e878c2bdbeaee988c8e2</id>
<content type='text'>
Got accidently dropped when 2+1 level support was added.

Fixes: 6a42fd6fbf534096 ("drm/amdgpu: implement 2+1 PD support for Raven v3")
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: shadow in shadow_list without tbo.mem.start cause page fault in sriov TDR</title>
<updated>2019-04-12T16:23:49Z</updated>
<author>
<name>wentalou</name>
<email>Wentao.Lou@amd.com</email>
</author>
<published>2019-04-12T07:01:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b575f10dbd6f84c2c8744ff1f486bfae1e4f6f38'/>
<id>urn:sha1:b575f10dbd6f84c2c8744ff1f486bfae1e4f6f38</id>
<content type='text'>
shadow was added into shadow_list by amdgpu_bo_create_shadow.
meanwhile, shadow-&gt;tbo.mem was not fully configured.
tbo.mem would be fully configured by amdgpu_vm_sdma_map_table until calling amdgpu_vm_clear_bo.
If sriov TDR occurred between amdgpu_bo_create_shadow and amdgpu_vm_sdma_map_table,
amdgpu_device_recover_vram would deal with shadow without tbo.mem.start.

Signed-off-by: Wentao Lou &lt;Wentao.Lou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: extending AUX SW Timeout</title>
<updated>2019-04-11T15:03:08Z</updated>
<author>
<name>Martin Leung</name>
<email>martin.leung@amd.com</email>
</author>
<published>2019-03-26T17:14:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f4bbebf8e7eb4d294b040ab2d2ba71e70e69b930'/>
<id>urn:sha1:f4bbebf8e7eb4d294b040ab2d2ba71e70e69b930</id>
<content type='text'>
[Why]
AUX takes longer to reply when using active DP-DVI dongle on some asics
resulting in up to 2000+ us edid read (timeout).

[How]
1. Adjust AUX poll to match spec
2. Extend the SW timeout. This does not affect normal
operation since we exit the loop as soon as AUX acks.

Signed-off-by: Martin Leung &lt;martin.leung@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Joshua Aberback &lt;Joshua.Aberback@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix negative cursor pos programming (v2)</title>
<updated>2019-04-08T15:33:40Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2019-02-01T14:36:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bd13b2b874eceb4677cd26eebdc5f45cc52fa400'/>
<id>urn:sha1:bd13b2b874eceb4677cd26eebdc5f45cc52fa400</id>
<content type='text'>
[Why]
If the cursor pos passed from DM is less than the plane_state-&gt;dst_rect
top left corner then the unsigned cursor pos wraps around to a large
positive number since cursor pos is a u32.

There was an attempt to guard against this in hubp1_cursor_set_position
by checking the src_x_offset and src_y_offset and offseting the
cursor hotspot within hubp1_cursor_set_position.

However, the cursor position itself is still being programmed
incorrectly as a large value.

This manifests itself visually as the cursor disappearing or containing
strange artifacts near the middle of the screen on raven.

[How]
Don't subtract the destination rect top left corner from the pos but
add it to the hotspot instead. This happens before the pos gets
passed into hubp1_cursor_set_position.

This achieves the same result but avoids the subtraction wrap around.
With this fix the original cursor programming logic can be used again.

v2: add hunk that got dropped accidently when this patch was originally
committed. (Alex)
Fixes: 0921c41e1902831 ("drm/amd/display: Fix negative cursor pos programming")

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Acked-by: Murton Liu &lt;Murton.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix cursor black issue</title>
<updated>2019-04-04T15:23:15Z</updated>
<author>
<name>tiancyin</name>
<email>tianci.yin@amd.com</email>
</author>
<published>2019-04-01T02:15:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c1cefe115d1cdc460014483319d440b2f0d07c68'/>
<id>urn:sha1:c1cefe115d1cdc460014483319d440b2f0d07c68</id>
<content type='text'>
[Why]
the member sdr_white_level of struct dc_cursor_attributes was not
initialized, then the random value result that
dcn10_set_cursor_sdr_white_level() set error hw_scale value 0x20D9(normal
value is 0x3c00), this cause the black cursor issue.

[how]
just initilize the obj of struct dc_cursor_attributes to zero to avoid
the random value.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Tianci Yin &lt;tianci.yin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: amdgpu_device_recover_vram always failed if only one node in shadow_list</title>
<updated>2019-04-04T15:22:06Z</updated>
<author>
<name>wentalou</name>
<email>Wentao.Lou@amd.com</email>
</author>
<published>2019-04-02T09:13:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1712fb1a2f6829150032ac76eb0e39b82a549cfb'/>
<id>urn:sha1:1712fb1a2f6829150032ac76eb0e39b82a549cfb</id>
<content type='text'>
amdgpu_bo_restore_shadow would assign zero to r if succeeded.
r would remain zero if there is only one node in shadow_list.
current code would always return failure when r &lt;= 0.
restart the timeout for each wait was a rather problematic bug as well.
The value of tmo SHOULD be changed, otherwise we wait tmo jiffies on each loop.

Signed-off-by: Wentao Lou &lt;Wentao.Lou@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Adjust IB test timeout for XGMI configuration</title>
<updated>2019-04-04T15:21:14Z</updated>
<author>
<name>shaoyunl</name>
<email>shaoyun.liu@amd.com</email>
</author>
<published>2019-04-01T20:09:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d4162c61e253177936fcfe6c29f7b224d9a1efb8'/>
<id>urn:sha1:d4162c61e253177936fcfe6c29f7b224d9a1efb8</id>
<content type='text'>
On XGMI configuration the ib test may take longer to finish

Signed-off-by: shaoyunl &lt;shaoyun.liu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Add picasso pci id</title>
<updated>2019-04-04T15:20:34Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-04-03T17:30:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e7ad88553aa1d48e950ca9a4934d246c1bee4be4'/>
<id>urn:sha1:e7ad88553aa1d48e950ca9a4934d246c1bee4be4</id>
<content type='text'>
Picasso is a new raven variant.

Reviewed-by: Kent Russell &lt;kent.russell@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: remove unnecessary rlc reset function on gfx9</title>
<updated>2019-04-02T21:23:16Z</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2019-04-01T10:08:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d939f44d4a7f910755165458da20407d2139f581'/>
<id>urn:sha1:d939f44d4a7f910755165458da20407d2139f581</id>
<content type='text'>
The rlc reset function is not necessary during gfx9 initialization/resume phase.
And this function would even cause rlc fw loading failed on some gfx9 ASIC.
Remove this function safely with verification well on Vega/Raven platform.

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
