<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/amd, branch v6.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-06-13T21:16:35Z</updated>
<entry>
<title>drm/amd/display: limit DPIA link rate to HBR3</title>
<updated>2023-06-13T21:16:35Z</updated>
<author>
<name>Peichen Huang</name>
<email>peichen.huang@amd.com</email>
</author>
<published>2023-05-31T05:36:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7c5835bcb9176df94683396f1c0e5df6bf5094b3'/>
<id>urn:sha1:7c5835bcb9176df94683396f1c0e5df6bf5094b3</id>
<content type='text'>
[Why]
DPIA doesn't support UHBR, driver should not enable UHBR
for dp tunneling

[How]
limit DPIA link rate to HBR3

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Signed-off-by: Peichen Huang &lt;peichen.huang@amd.com&gt;
Reviewed-by: Mustapha Ghaddar &lt;Mustapha.Ghaddar@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix the system hang while disable PSR</title>
<updated>2023-06-13T21:14:52Z</updated>
<author>
<name>Tom Chung</name>
<email>chiahsuan.chung@amd.com</email>
</author>
<published>2023-05-29T10:00:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ea2062dd1f0384ae1b136d333ee4ced15bedae38'/>
<id>urn:sha1:ea2062dd1f0384ae1b136d333ee4ced15bedae38</id>
<content type='text'>
[Why]
When the PSR enabled. If you try to adjust the timing parameters,
it may cause system hang. Because the timing mismatch with the
DMCUB settings.

[How]
Disable the PSR before adjusting timing parameters.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Signed-off-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Reviewed-by: Wayne Lin &lt;Wayne.Lin@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: edp do not add non-edid timings</title>
<updated>2023-06-13T21:14:09Z</updated>
<author>
<name>Hersen Wu</name>
<email>hersenxs.wu@amd.com</email>
</author>
<published>2023-05-25T12:37:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e749dd10e5f292061ad63d2b030194bf7d7d452c'/>
<id>urn:sha1:e749dd10e5f292061ad63d2b030194bf7d7d452c</id>
<content type='text'>
[Why] most edp support only timings from edid. applying
non-edid timings, especially those timings out of edp
bandwidth, may damage edp.

[How] do not add non-edid timings for edp.

Cc: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Cc: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Signed-off-by: Hersen Wu &lt;hersenxs.wu@amd.com&gt;
Reviewed-by: Roman Li &lt;roman.li@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM in large bar system"</title>
<updated>2023-06-13T21:12:41Z</updated>
<author>
<name>Arunpravin Paneer Selvam</name>
<email>Arunpravin.PaneerSelvam@amd.com</email>
</author>
<published>2023-06-09T13:18:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=34e5a54327dce5033582f3609eb54812a8c61b90'/>
<id>urn:sha1:34e5a54327dce5033582f3609eb54812a8c61b90</id>
<content type='text'>
This reverts commit c105518679b6e87232874ffc989ec403bee59664.

This patch disables the TOPDOWN flag for APU and few dGPU cards
which has the VRAM size equal to the BAR size.

When we enable the TOPDOWN flag, we get the free blocks at
the highest available memory region and we don't split the
lower order blocks. This change is required to keep off
the fragmentation related issues particularly in ASIC
which has VRAM space &lt;= 500MiB

Hence, we are reverting this patch.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2270
Signed-off-by: Arunpravin Paneer Selvam &lt;Arunpravin.PaneerSelvam@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: vcn_4_0 set instance 0 init sched score to 1</title>
<updated>2023-06-13T21:08:42Z</updated>
<author>
<name>Sonny Jiang</name>
<email>sonjiang@amd.com</email>
</author>
<published>2023-06-06T21:18:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9db5ec1ceb5303398ec4f899d691073d531257c3'/>
<id>urn:sha1:9db5ec1ceb5303398ec4f899d691073d531257c3</id>
<content type='text'>
Only vcn0 can process AV1 codecx. In order to use both vcn0 and
vcn1 in h264/265 transcode to AV1 cases, set vcn0 sched score to 1
at initialization time.

Signed-off-by: Sonny Jiang &lt;sonjiang@amd.com&gt;
Reviewed-by: Leo Liu &lt;leo.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
</entry>
<entry>
<title>drm/amd/pm: workaround for compute workload type on some skus</title>
<updated>2023-06-13T21:05:49Z</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2023-06-08T14:07:11Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7ca302d488f80cf4529620acc1c545f9022d8bb8'/>
<id>urn:sha1:7ca302d488f80cf4529620acc1c545f9022d8bb8</id>
<content type='text'>
On smu 13.0.0, the compute workload type cannot be set on all the skus
due to some other problems. This workaround is to make sure compute workload type
can also run on some specific skus.

v2: keep the variable consistent

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Acked-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Feifei Xu &lt;Feifei.Xu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
</content>
</entry>
<entry>
<title>drm/amd: Tighten permissions on VBIOS flashing attributes</title>
<updated>2023-06-13T21:04:51Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-06-07T06:45:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7ab1a4913d0051cf5196ef7987b5fa42c25e13b6'/>
<id>urn:sha1:7ab1a4913d0051cf5196ef7987b5fa42c25e13b6</id>
<content type='text'>
Non-root users shouldn't be able to try to trigger a VBIOS flash
or query the flashing status.  This should be reserved for users with the
appropriate permissions.

Cc: stable@vger.kernel.org
Fixes: 8424f2ccb3c0 ("drm/amdgpu/psp: Add vbflash sysfs interface support")
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Make sure image is written to trigger VBIOS image update flow</title>
<updated>2023-06-13T21:04:45Z</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-06-07T06:41:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3eb1a3a04056ba3df3205e169b8acc9da0c65a94'/>
<id>urn:sha1:3eb1a3a04056ba3df3205e169b8acc9da0c65a94</id>
<content type='text'>
The VBIOS image update flow requires userspace to:
1) Write the image to `psp_vbflash`
2) Read `psp_vbflash`
3) Poll `psp_vbflash_status` to check for completion

If userspace reads `psp_vbflash` before writing an image, it's
possible that it causes problems that can put the dGPU into an invalid
state.

Explicitly check that an image has been written before letting a read
succeed.

Cc: stable@vger.kernel.org
Fixes: 8424f2ccb3c0 ("drm/amdgpu/psp: Add vbflash sysfs interface support")
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add missing radeon secondary PCI ID</title>
<updated>2023-06-13T21:02:51Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2023-06-06T15:14:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e61f67749b351c19455ce3085af2ae9af80023bc'/>
<id>urn:sha1:e61f67749b351c19455ce3085af2ae9af80023bc</id>
<content type='text'>
0x5b70 is a missing RV370 secondary id.  Add it so
we don't try and probe it with amdgpu.

Cc: michel@daenzer.net
Reviewed-by: Michel Dänzer &lt;mdaenzer@redhat.com&gt;
Tested-by: Michel Dänzer &lt;mdaenzer@redhat.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>drm/amdgpu: Implement gfx9 patch functions for resubmission</title>
<updated>2023-06-13T20:58:23Z</updated>
<author>
<name>Jiadong Zhu</name>
<email>Jiadong.Zhu@amd.com</email>
</author>
<published>2023-05-25T10:42:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5b711e7f9c73e5ff44d6ac865711d9a05c2a0360'/>
<id>urn:sha1:5b711e7f9c73e5ff44d6ac865711d9a05c2a0360</id>
<content type='text'>
Patch the packages including CONTEXT_CONTROL and WRITE_DATA for gfx9
during the resubmission scenario.

Signed-off-by: Jiadong Zhu &lt;Jiadong.Zhu@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.3.x
</content>
</entry>
</feed>
