<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/drm_cache.c, branch v4.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.7'/>
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<updated>2016-03-31T11:35:09Z</updated>
<entry>
<title>x86/cpufeature: Remove cpu_has_clflush</title>
<updated>2016-03-31T11:35:09Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2016-03-29T15:41:59Z</published>
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<id>urn:sha1:906bf7fda2c9cf5c1762ec607943ed54b6c5b203</id>
<content type='text'>
Use the fast variant in the DRM code.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Cc: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: dri-devel@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Link: http://lkml.kernel.org/r/1459266123-21878-7-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar &lt;mingo@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()</title>
<updated>2015-06-19T15:25:17Z</updated>
<author>
<name>Chris Wilson</name>
<email>chris@chris-wilson.co.uk</email>
</author>
<published>2015-06-10T14:58:01Z</published>
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<id>urn:sha1:afcd950cafea6e27b739fe7772cbbeed37d05b8b</id>
<content type='text'>
As the clflush operates on cache lines, and we can flush any byte
address, in order to flush all bytes given in the range we issue an
extra clflush on the last byte to ensure the last cacheline is flushed.
We can can the iteration to be over the actual cache lines to avoid this
double clflush on the last byte.

Signed-off-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Cc: Imre Deak &lt;imre.deak@intel.com&gt;
Reviewed-by: Imre Deak &lt;imre.deak@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm/cache: Use wbinvd helpers</title>
<updated>2014-12-16T07:56:55Z</updated>
<author>
<name>Ben Widawsky</name>
<email>ben@bwidawsk.net</email>
</author>
<published>2014-12-15T20:26:46Z</published>
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<id>urn:sha1:b04d4a38c0691e4467fa2988b6fe481bf759daaf</id>
<content type='text'>
When the original drm code was written there were no centralized functions for
doing a coordinated wbinvd across all CPUs. Now (since 2010) there are, so use
them instead of rolling a new one.

v2: On x86 UP systems the wbinvd_on_all_cpus() is defined as a static inline in
smp.h. We must therefore include this file so we don't get compiler errors.
This error was found by 0-DAY kernel test infrastructure. We only need this for
x86.

Cc: Intel GFX &lt;intel-gfx@lists.freedesktop.org&gt;
Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt; (v1)
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm: Missed clflushopt in drm_clflush_virt_range</title>
<updated>2014-06-02T07:57:31Z</updated>
<author>
<name>Ross Zwisler</name>
<email>ross.zwisler@linux.intel.com</email>
</author>
<published>2014-05-14T15:41:12Z</published>
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<id>urn:sha1:7927096868061ff10fdb33b295dc0bcfebe2b35b</id>
<content type='text'>
With this commit:

2a0788dc9bc4 x86: Use clflushopt in drm_clflush_virt_range

If clflushopt is available on the system, we use it instead of clflush
in drm_clflush_virt_range.  There were two calls to clflush in this
function, but only one was changed to clflushopt.  This patch changes
the other clflush call to clflushopt.

Signed-off-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Reported-by: Matthew Wilcox &lt;matthew.r.wilcox@intel.com&gt;

Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: dri-devel@lists.freedesktop.org
Cc: H Peter Anvin &lt;h.peter.anvin@intel.com&gt;
Cc: Ingo Molnar &lt;mingo@kernel.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-next-2014-04-16' of git://anongit.freedesktop.org/drm-intel into drm-next</title>
<updated>2014-04-30T23:11:37Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2014-04-30T23:11:37Z</published>
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<id>urn:sha1:885ac04ab3a226d28147853d6d98eee3897a5636</id>
<content type='text'>
drm-intel-next-2014-04-16:
- vlv infoframe fixes from Jesse
- dsi/mipi fixes from Shobhit
- gen8 pageflip fixes for LRI/SRM from Damien
- cmd parser fixes from Brad Volkin
- some prep patches for CHV, DRRS, ...
- and tons of little things all over
drm-intel-next-2014-04-04:
- cmd parser for gen7 but only in enforcing and not yet granting mode - the
  batch copying stuff is still missing. Also performance is a bit ... rough
  (Brad Volkin + OACONTROL fix from Ken).
- deprecate UMS harder (i.e. CONFIG_BROKEN)
- interrupt rework from Paulo Zanoni
- runtime PM support for bdw and snb, again from Paulo
- a pile of refactorings from various people all over the place to prep for new
  stuff (irq reworks, power domain polish, ...)

drm-intel-next-2014-04-04:
- cmd parser for gen7 but only in enforcing and not yet granting mode - the
  batch copying stuff is still missing. Also performance is a bit ... rough
  (Brad Volkin + OACONTROL fix from Ken).
- deprecate UMS harder (i.e. CONFIG_BROKEN)
- interrupt rework from Paulo Zanoni
- runtime PM support for bdw and snb, again from Paulo
- a pile of refactorings from various people all over the place to prep for new
  stuff (irq reworks, power domain polish, ...)

Conflicts:
	drivers/gpu/drm/i915/i915_gem_context.c
</content>
</entry>
<entry>
<title>drm: Make drm_clflush_virt_range() void*</title>
<updated>2014-04-01T20:58:29Z</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2014-04-01T09:59:08Z</published>
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<id>urn:sha1:c2d15359c4b5476c181d8a51bdeba4cead15c120</id>
<content type='text'>
Currently drm_cflush_virt_rage() takes a char* so the caller probably
has to do pointless casting to avoid compiler warnings. Make the
argument void* instead to avoid such issues.

v2: Use void* arithmetic (Chris)

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Reviewed-by: Chris Wilson &lt;chris@chris-wilson.co.uk&gt;
Acked-by: Dave Airlie &lt;airlied@redhat.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>x86: Use clflushopt in drm_clflush_virt_range</title>
<updated>2014-02-27T16:26:31Z</updated>
<author>
<name>Ross Zwisler</name>
<email>ross.zwisler@linux.intel.com</email>
</author>
<published>2014-02-26T19:06:52Z</published>
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<id>urn:sha1:2a0788dc9bc46789ec98aea0f30c6fb420196b12</id>
<content type='text'>
If clflushopt is available on the system, use it instead of clflush in
drm_clflush_virt_range.

Signed-off-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Link: http://lkml.kernel.org/r/1393441612-19729-5-git-send-email-ross.zwisler@linux.intel.com
Signed-off-by: H. Peter Anvin &lt;hpa@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: Use clflushopt in drm_clflush_page</title>
<updated>2014-02-27T16:26:20Z</updated>
<author>
<name>Ross Zwisler</name>
<email>ross.zwisler@linux.intel.com</email>
</author>
<published>2014-02-26T19:06:51Z</published>
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<id>urn:sha1:2a0c772f1967565d5b71a98012e74d5a7bddc1c4</id>
<content type='text'>
If clflushopt is available on the system, use it instead of clflush in
drm_clflush_page.

Signed-off-by: Ross Zwisler &lt;ross.zwisler@linux.intel.com&gt;
Link: http://lkml.kernel.org/r/1393441612-19729-4-git-send-email-ross.zwisler@linux.intel.com
Signed-off-by: H. Peter Anvin &lt;hpa@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>lib/scatterlist: sg_page_iter: support sg lists w/o backing pages</title>
<updated>2013-03-27T16:13:44Z</updated>
<author>
<name>Imre Deak</name>
<email>imre.deak@intel.com</email>
</author>
<published>2013-03-26T13:14:18Z</published>
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<id>urn:sha1:2db76d7c3c6db93058f983c8240f7c7c25e87ee6</id>
<content type='text'>
The i915 driver uses sg lists for memory without backing 'struct page'
pages, similarly to other IO memory regions, setting only the DMA
address for these. It does this, so that it can program the HW MMU
tables in a uniform way both for sg lists with and without backing pages.

Without a valid page pointer we can't call nth_page to get the current
page in __sg_page_iter_next, so add a helper that relevant users can
call separately. Also add a helper to get the DMA address of the current
page (idea from Daniel).

Convert all places in i915, to use the new API.

Signed-off-by: Imre Deak &lt;imre.deak@intel.com&gt;
Reviewed-by: Damien Lespiau &lt;damien.lespiau@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
<entry>
<title>drm: handle compact dma scatter lists in drm_clflush_sg()</title>
<updated>2013-03-19T08:50:22Z</updated>
<author>
<name>Imre Deak</name>
<email>imre.deak@intel.com</email>
</author>
<published>2013-02-18T17:28:01Z</published>
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<id>urn:sha1:f5ddf69736fb328800ccd1a06fe69ad2e830adbe</id>
<content type='text'>
So far the assumption was that each scatter list entry contains a single
page. This might not hold in the future, when we'll introduce compact
scatter lists, so prepare for this here.

Reference: http://www.spinics.net/lists/dri-devel/msg33917.html
Signed-off-by: Imre Deak &lt;imre.deak@intel.com&gt;
Acked-by: Dave Airlie &lt;airlied@gmail.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
</content>
</entry>
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