linux/drivers/gpu/drm/msm/Makefile, branch master

drm/msm/a8xx: Preemption support for A840

2026-03-31T20:47:30Z

The programing sequence related to preemption is unchanged from A7x. But there is some code churn due to register shuffling in A8x. So, split out the common code into a header file for code sharing and add/update additional changes required to support preemption feature on A8x GPUs. Finally, enable the preemption quirk in A840's catalog to enable this feature. Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/714682/ Message-ID: <20260327-a8xx-gpu-batch2-v2-15-2b53c38d2101@oss.qualcomm.com> Signed-off-by: Rob Clark

drm/msm/dpu: Add Kaanapali SSPP sub-block support

2026-01-21T00:07:23Z

Add support for Kaanapali platform SSPP sub-blocks, which introduce structural changes including register additions, removals, and relocations. Add the new common and rectangle blocks, and update register definitions and handling to ensure compatibility with DPU v13.0. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/698712/ Link: https://lore.kernel.org/r/20260115092749.533-11-yuanjie.yang@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

drm/msm/adreno: Introduce A8x GPU Support

2025-11-18T17:04:01Z

A8x is the next generation of Adreno GPUs, featuring a significant hardware design change. A major update to the design is the introduction of Slice architecture. Slices are sort of mini-GPUs within the GPU which are more independent in processing Graphics and compute workloads. Also, in addition to the BV and BR pipe we saw in A7x, CP has more concurrency with additional pipes. From a software interface perspective, these changes have a significant impact on the KMD side. First, the GPU register space has been extensively reorganized. Second, to avoid a register space explosion caused by the new slice architecture and additional pipes, many registers are now virtualized, instead of duplicated as in A7x. KMD must configure an aperture register with the appropriate slice and pipe ID before accessing these virtualized registers. Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689019/ Message-ID: <20251118-kaana-gpu-support-v4-14-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark

drm/msm/a6xx: Sync latest register definitions

2025-11-18T17:04:00Z

Sync the latest register definitions from Mesa which includes the updates for A8x family. Co-developed-by: Rob Clark Signed-off-by: Rob Clark Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/689009/ Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com>

drm/msm: make it possible to disable KMS-related code.

2025-07-05T14:13:35Z

If the Adreno device is used in a headless mode, there is no need to build all KMS components. Build corresponding parts conditionally, only selecting them if modeset support is actually required. Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/662581/ Signed-off-by: Rob Clark

drm/msm: Update register xml

2025-07-05T00:48:39Z

Sync register xml from mesa commit eb3e0b7164a3 ("freedreno/a6xx: Split descriptors out into their own file"). Signed-off-by: Rob Clark Acked-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/662470/

drm/msm: Extract out syncobj helpers

2025-07-05T00:48:37Z

We'll be re-using these for the VM_BIND ioctl. Also, rename a few things in the uapi header to reflect that syncobj use is not specific to the submit ioctl. Signed-off-by: Rob Clark Signed-off-by: Rob Clark Tested-by: Antonino Maniscalco Reviewed-by: Antonino Maniscalco Patchwork: https://patchwork.freedesktop.org/patch/661512/

drm/msm/dp: drop the msm_dp_catalog module

2025-07-04T13:35:19Z

Now as the msm_dp_catalog module became nearly empty, drop it, accessing registers directly from the corresponding submodules. Reviewed-by: Stephen Boyd Tested-by: Stephen Boyd # sc7180-trogdor Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/654332/ Link: https://lore.kernel.org/r/20250518-fd-dp-audio-fixup-v6-11-2f0ec3ec000d@oss.qualcomm.com

drm/msm/mdp4: switch LVDS to use drm_bridge/_connector

2025-05-01T22:14:11Z

LVDS support in MDP4 driver makes use of drm_connector directly. However LCDC encoder and LVDS connector are wrappers around drm_panel. Switch them to use drm_panel_bridge/drm_bridge_connector. This allows using standard interface for the drm_panel and also inserting additional bridges between encoder and panel. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/650290/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-6-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov

drm/msm/dpu: Add dpu_hw_cwb abstraction for CWB block

2024-12-24T20:04:59Z

The CWB mux has its own registers and set of operations. Add dpu_hw_cwb abstraction to allow driver to configure the CWB mux. Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/629254/ Link: https://lore.kernel.org/r/20241216-concurrent-wb-v4-12-fe220297a7f0@quicinc.com [DB: added #include ] Signed-off-by: Dmitry Baryshkov