Merge tag 'drm-msm-next-2019-11-05' of https://gitlab.freedesktop.org/drm/msm into drm-next

2019-12-02T00:21:12Z

+ OCMEM support to enable the couple generations that had shared OCMEM rather than GMEM exclusively for the GPU (late a3xx and I think basically all of a4xx). Bjorn and Brian decided to land this through the drm tree to avoid having to coordinate merge requests. + a510 support, and various associated display support + the usual misc cleanups and fixes Signed-off-by: Dave Airlie From: Rob Clark Link: https://patchwork.freedesktop.org/patch/msgid/

drm/msm: fix memleak on release

2019-11-13T20:34:15Z

If a process is interrupted while accessing the "gpu" debugfs file and the drm device struct_mutex is contended, release() could return early and fail to free related resources. Note that the return value from release() is ignored. Fixes: 4f776f4511c7 ("drm/msm/gpu: Convert the GPU show function to use the GPU state") Cc: stable # 4.18 Cc: Jordan Crouse Cc: Rob Clark Reviewed-by: Rob Clark Signed-off-by: Johan Hovold Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20191010131333.23635-2-johan@kernel.org

drm: msm: a6xx: fix debug bus register configuration

2019-11-06T17:45:18Z

Fix the cx debugbus related register configuration, to collect accurate bus data during gpu snapshot. This helps with complete snapshot dump and also complete proper GPU recovery. Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state") Reviewed-by: Rob Clark Signed-off-by: Sharat Masetty Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/339165

drm/msm/adreno: Add support for Adreno 510 GPU

2019-11-04T21:18:31Z

The Adreno 510 GPU is a stripped version of the Adreno 5xx, found in low-end SoCs like 8x56 and 8x76, which has 256K of GMEM, with no GPMU nor ZAP. Also, since the Adreno 5xx part of this driver seems to be developed with high-end Adreno GPUs in mind, and since this is a lower end one, add a comment making clear which GPUs which support is not implemented yet is not using the GPMU related hw init code, so that future developers will not go crazy with that. By the way, the lower end Adreno GPUs with no GPMU are: A505/A506/A510 (usually no ZAP firmware) A508/A509/A512 (usually with ZAP firmware) Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Clark

drm/msm/dsi: Add configuration for 8x76

2019-11-04T21:18:31Z

MSM8976, MSM8976 and APQ variants have DSI version 3:10040002 (DSI 6G V1.4.2), featuring two DSIs. They need three clocks (mdp_core, iface, bus), one GDSC and two vregs, VDDA at 1.2V and VDDIO at 1.8V. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Clark

drm/msm/dsi: Add configuration for 28nm PLL on family B

2019-11-04T21:17:42Z

The 28nm PLL has a different iospace on MSM/APQ family B SoCs: add a new configuration and use it when the DT reports the "qcom,dsi-phy-28nm-hpm-fam-b" compatible. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Clark

drm/msm/mdp5: Add configuration for msm8x76

2019-11-04T21:17:42Z

Add the configuration entries for the MDP5 v1.11, found on MSM8956, MSM8976 and APQ variants. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Clark

drm/msm/mdp5: Add optional TBU and TBU_RT clocks

2019-11-02T17:20:41Z

Some SoCs, like MSM8956/8976 (and APQ variants), do feature these clocks and we need to enable them in order to get both of the hw (mdp5/rot) Translation Buffer Units (TBUs) to properly work. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Clark

drm/msm: always dump buffer base/size

2019-11-02T16:43:24Z

Even if we are not dumping the buffer's contents, it is useful to log their base address and size. This makes it easier to see when different gpu pointers point to a single buffer, for example higher mipmap levels of a single texture. Signed-off-by: Rob Clark

drm/msm: fix rd dumping for split-IB1