linux/drivers/gpu/drm/xe/display, branch master

drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

2026-03-24T13:29:12Z

Now that we have implemented all the related missing bits we can enable the AuxCCS compressed modifiers which were disabled in cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe"). Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P: [PLANE:32:plane 1A]: type=PRI uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=28 hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000 Display is working fine - no artefacts, no DMAR/PIPE faults. v2: * Adjust patch title. (Rodrigo) v3: * Complete rewrite based on the display parent interface. Signed-off-by: Tvrtko Ursulin References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe") Cc: Jani Nikula Cc: José Roberto de Souza Cc: Juha-Pekka Heikkila Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/20260324084018.20353-13-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

drm/xe/display: Add support for AuxCCS

2026-03-24T13:29:11Z

Add support for mapping the auxiliary CCS buffer into the DPT page tables. This will allow for better power efficiency by enabling the render compression frame buffer modifiers such as I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS in a following patch. Signed-off-by: Tvrtko Ursulin Cc: Juha-Pekka Heikkila Cc: Michael J. Ruhl Cc: Rodrigo Vivi Cc: Thomas Hellström Cc: Maarten Lankhorst Reviewed-by: Uma Shankar Link: https://patch.msgid.link/20260324084018.20353-12-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

drm/xe/display: Respect remapped plane alignment

2026-03-24T13:29:11Z

Instead of assuming PAGE_SIZE alignment between the remapped planes respect the value set in the struct intel_remapped_info. Signed-off-by: Tvrtko Ursulin Cc: Juha-Pekka Heikkila Cc: Michael J. Ruhl Cc: Rodrigo Vivi Cc: Thomas Hellström Cc: Maarten Lankhorst Reviewed-by: Uma Shankar Link: https://patch.msgid.link/20260324084018.20353-11-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

drm/xe/display: Change write_dpt_remapped_tiled function signature

2026-03-24T13:29:11Z

In preparation for adding support for the auxccs plane lets change the function signature of write_dpt_remapped_tiled(). This will enable a tidier way of extending it subsequent patches. Signed-off-by: Tvrtko Ursulin Cc: Juha-Pekka Heikkila Cc: Michael J. Ruhl Cc: Rodrigo Vivi Cc: Thomas Hellström Cc: Maarten Lankhorst Cc: Uma Shankar Reviewed-by: Uma Shankar Link: https://patch.msgid.link/20260324084018.20353-10-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

drm/xe/display: Move remapped plane loop out of __xe_pin_fb_vma_dpt

2026-03-24T13:29:11Z

In preparation for adding support for the auxccs plane lets move the plane iteration loop to its own function. Signed-off-by: Tvrtko Ursulin Cc: Juha-Pekka Heikkila Cc: Michael J. Ruhl Cc: Rodrigo Vivi Cc: Thomas Hellström Cc: Maarten Lankhorst Reviewed-by: Uma Shankar Link: https://patch.msgid.link/20260324084018.20353-9-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

drm/xe: Use write-combine mapping when populating DPT

2026-03-24T13:29:10Z

The fallback case for DPT backing store is a buffer object in system memory buffer, which by default use a write-back CPU caching policy. If this fallback gets triggered, and since there is currently no flushing, the DPT writes made when pinning a buffer to display are not guaranteed to be seen by the display engine. To fix this, since both the local memory and the stolen memory DPT placements already use write-combine, let us make the system memory option follow suit by passing down the appropriate flag. Signed-off-by: Tvrtko Ursulin Suggested-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/20260324084018.20353-3-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

drm/xe: Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC

2026-03-24T13:29:10Z

Rename XE_BO_FLAG_SCANOUT to XE_BO_FLAG_FORCE_WC so that the usage of the flag can legitimately be expanded to more than just the actual frame- buffer objects. Signed-off-by: Tvrtko Ursulin Suggested-by: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Link: https://patch.msgid.link/20260324084018.20353-2-tvrtko.ursulin@igalia.com Signed-off-by: Rodrigo Vivi

Merge tag 'drm-intel-next-2026-03-16' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

2026-03-17T05:44:26Z

[airlied: fixed conflict with xe tree] drm/i915 feature pull for v7.1: Features and functionality: - C10/C20/LT PHY PLL divider verification (Mika) - Use trans push mechanism to generate PSR frame change event on LNL+ (Jouni) - Account for DSC bubble overhead for horizontal slices (Ankit, Chaitanya) Refactoring and cleanups: - Refactor DP DSC slice config computation (Imre) - Use GVT versions of register helper macros for GVT MMIO table (Ankit) - C10/C20/LT PHY PLL computation refactoring (Mika) - VGA decode refactoring and related fixes/cleanups (Ville) - Move DSB buffer buffer implementation to display parent interface (Jani) - Move error interrupt capture to display irq snapshot (Jani) - Move pcode calls to display parent interface (Jani) - Reduce GVT dependency on display headers (Jani) - Compute config and mode valid refactoring for DSC (Ankit) - Stop using i915 core register headers in display (Uma) - Refactor DPT, move i915 parts to display parent interface (Jani) - Refactor gen2-4 overlay, move to display parent interface (Ville) - Refactor masked field register macro helpers, move to shared headers (Jani) - Convert a number of workaround checks to the new workaround framework (Luca) - Refactor and move frontbuffer calls to display parent interface (Jani) - Add VMA calls to display parent interface (Jani) - Refactor stolen memory allocation decisions (Vinod, Ville) - Clean up and unify workqueue usage (Marco Crivellari) - Preparation for UHBR DP tunnels (Imre) - Allow DSC passthrough modes during DP MST mode validation (Imre) - Move framebuffer bo interface to display parent interface (Jani) Fixes: - Plenty of DP SST HPD IRQ handling fixes (Imre) - DP AUX backlight and luminance control fixes (Suraj) - Respect VBT pipe joiner disable for eDP (Ankit) - Do not use CASF with joiner (Nemesa) - Clear C10/C20 PHY response read and error bit to avoid PHY hangs (Suraj) - Xe3p_LPD DMG clock gating, CDCLK, port sync workarounds (Suraj, Gustavo, Mitul) - Fix GVT error path (Michał) - Handle errors on DP DSC receiver cap reads (Suraj) - DSS clock gating workaround on MTL+ to avoid DSC corruption (Mika) - Skip state verification for LT PHY in TBT mode (Suraj) - Fix NULL pointer dereference on suspend when uc firmware not loaded (Rahul Bukte) - Fix an unlikely DMC state related NULL pointer dereference at probe (Imre) - Handle error returns from vga_get_uninterruptible() (Simon Richter) - Increase C10/C20/LT PHY timeouts to include SOC/OS turnaround (Arun) - Fix BIOS FB vs. stolen memory size check (Ville) - Fix LOBF to use computed guardband and set context latency (Ankit) - Handle modeset WW mutex lock failures due to contention properly (Imre) - Fix pipe BPP clamping due to HDR (Imre) - Fix stale state usage in DSC state computation (Imre) - Take HDCP 1.4 vs 2.x into account during link check (Suraj) - Fix forced link retrain handling in MST HPD IRQ handler (Imre) - Remove redundant warning on vcpi < 0 (Jonathan) Core changes: - iopoll: fix function parameter names in read_poll_timeout_atomic() (Randy Dunlap) Merges: - Backmerge drm-next for v7.0-rc1 (Jani) Signed-off-by: Dave Airlie From: Jani Nikula Link: https://patch.msgid.link/b14bb0f297b1750816cf5f342bde608e435655fa@intel.com

drm/{i915,xe}: move framebuffer bo to parent interface

2026-03-16T09:00:21Z

Add .framebuffer_init, .framebuffer_fini and .framebuffer_lookup to the bo parent interface. While they're about framebuffers, they're specifically about framebuffer objects, so the bo interface is a good enough fit, and there's no need to add another interface struct. Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/848d32a44bf844cba3d66e44ba9f20bea4a8352d.1773238670.git.jani.nikula@intel.com Signed-off-by: Jani Nikula

drm/{i915, xe}/bo: move display bo calls to parent interface

2026-03-16T09:00:21Z

Continue i915 and xe separation from display by moving the bo calls to the display parent interface. Instead of adding all these functions to intel_parent.[ch], reuse the now vacated intel_bo.[ch], and avoid mass renames to calls of these functions. This is similar to intel_display_rpm.[ch]. Make many of the hooks optional to avoid having to implement dummy functions in xe. Indeed now we can remove many of the existing dummy functions. Reviewed-by: Suraj Kandpal Link: https://patch.msgid.link/7899eef2ccf0cd603df69099df065226a0df917b.1773238670.git.jani.nikula@intel.com Signed-off-by: Jani Nikula