<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/drm/xe, branch for-next</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=for-next</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=for-next'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2025-01-16T19:03:11Z</updated>
<entry>
<title>drm/xe: Mark ComputeCS read mode as UC on iGPU</title>
<updated>2025-01-16T19:03:11Z</updated>
<author>
<name>Matthew Brost</name>
<email>matthew.brost@intel.com</email>
</author>
<published>2025-01-14T00:25:07Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b1231ff7ea0689d04040a44864c265bc11612fa8'/>
<id>urn:sha1:b1231ff7ea0689d04040a44864c265bc11612fa8</id>
<content type='text'>
RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
structure. Having this as WB blocks ULLS from being enabled. Change to
UC to unblock ULLS on iGPU.

v2:
 - Drop internal communications commnet, bspec is updated

Cc: Balasubramani Vivekanandan &lt;balasubramani.vivekanandan@intel.com&gt;
Cc: Michal Mrozek &lt;michal.mrozek@intel.com&gt;
Cc: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Cc: stable@vger.kernel.org
Fixes: 328e089bfb37 ("drm/xe: Leverage ComputeCS read L3 caching")
Signed-off-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Acked-by: Michal Mrozek &lt;michal.mrozek@intel.com&gt;
Reviewed-by: Stuart Summers &lt;stuart.summers@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250114002507.114087-1-matthew.brost@intel.com
(cherry picked from commit 758debf35b9cda5450e40996991a6e4b222899bd)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/oa: Add missing VISACTL mux registers</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2025-01-11T02:15:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=79a21fc921d7aafaf69d00b4938435b81bf66022'/>
<id>urn:sha1:79a21fc921d7aafaf69d00b4938435b81bf66022</id>
<content type='text'>
Add missing VISACTL mux registers required for some OA
config's (e.g. RenderPipeCtrl).

Fixes: cdf02fe1a94a ("drm/xe/oa/uapi: Add/remove OA config perf ops")
Cc: stable@vger.kernel.org
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250111021539.2920346-1-ashutosh.dixit@intel.com
(cherry picked from commit c26f22dac3449d8a687237cdfc59a6445eb8f75a)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: make change ccs_mode a synchronous action</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Maciej Patelczyk</name>
<email>maciej.patelczyk@intel.com</email>
</author>
<published>2024-12-11T11:17:27Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b26de02cf903b5182588c0df91a6e1b512f7d3f3'/>
<id>urn:sha1:b26de02cf903b5182588c0df91a6e1b512f7d3f3</id>
<content type='text'>
If ccs_mode is being modified via
   /sys/class/drm/cardX/device/tileY/gtY/ccs_mode
the asynchronous reset is triggered and the write returns immediately.

With that some test receive false information about number of CCS engines
or even fail if they proceed without delay after changing the ccs_mode.

Changing the ccs_mode change from async to sync to prevent failures in
tests.

Signed-off-by: Maciej Patelczyk &lt;maciej.patelczyk@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Fixes: f3bc5bb4d53d ("drm/xe: Allow userspace to configure CCS mode")
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241211111727.1481476-3-maciej.patelczyk@intel.com
Signed-off-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
(cherry picked from commit 480fb9806e2e073532f7786166287114c696b340)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: introduce xe_gt_reset and xe_gt_wait_for_reset</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Maciej Patelczyk</name>
<email>maciej.patelczyk@intel.com</email>
</author>
<published>2024-12-11T11:17:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5db89168c408871d306e9fb669e494a1444da8ee'/>
<id>urn:sha1:5db89168c408871d306e9fb669e494a1444da8ee</id>
<content type='text'>
Add synchronous version gt reset as there are few places where it
is expected.
Also add a wait helper to wait until gt reset is done.

Signed-off-by: Maciej Patelczyk &lt;maciej.patelczyk@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Fixes: f3bc5bb4d53d ("drm/xe: Allow userspace to configure CCS mode")
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241211111727.1481476-2-maciej.patelczyk@intel.com
Signed-off-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
(cherry picked from commit 155c77f45f63dd58a37eeb0896b0b140ab785836)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/guc: Adding steering info support for GuC register lists</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Jesus Narvaez</name>
<email>jesus.narvaez@intel.com</email>
</author>
<published>2024-12-12T19:01:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=64192bb2e52d48cfccd8373b0ad565bb9ce3d2e6'/>
<id>urn:sha1:64192bb2e52d48cfccd8373b0ad565bb9ce3d2e6</id>
<content type='text'>
The guc_mmio_reg interface supports steering, but it is currently not
implemented. This will allow the GuC to control steering of MMIO
registers after save-restore and avoid reading from fused off MCR
register instances.

Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Signed-off-by: Jesus Narvaez &lt;jesus.narvaez@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Cc: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Cc: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Reviewed-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Signed-off-by: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241212190100.3768068-1-jesus.narvaez@intel.com
(cherry picked from commit ee5a1321df90891d59d83b7c9d5b6c5b755d059d)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/dg1: Fix power gate sequence.</title>
<updated>2025-01-09T09:38:56Z</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2024-12-19T23:55:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b84e1cd22f8a8c03b7b1051372560c7017c8be92'/>
<id>urn:sha1:b84e1cd22f8a8c03b7b1051372560c7017c8be92</id>
<content type='text'>
sub-pipe PG is not present on DG1. Setting these bits can disable
other power gates and cause GPU hangs on video playbacks.

VLK: 16314, 4304

Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381
Cc: Vinay Belgaumkar &lt;vinay.belgaumkar@intel.com&gt;
Cc: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Reviewed-by: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241219235536.454270-1-rodrigo.vivi@intel.com
Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
(cherry picked from commit 2f12e9c029315c1400059b2e7fdf53117c09c3a9)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: Fix tlb invalidation when wedging</title>
<updated>2025-01-09T09:38:56Z</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@intel.com</email>
</author>
<published>2025-01-03T00:11:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9ab4981552930a9c45682d62424ba610edc3992d'/>
<id>urn:sha1:9ab4981552930a9c45682d62424ba610edc3992d</id>
<content type='text'>
If GuC fails to load, the driver wedges, but in the process it tries to
do stuff that may not be initialized yet. This moves the
xe_gt_tlb_invalidation_init() to be done earlier: as its own doc says,
it's a software-only initialization and should had been named with the
_early() suffix.

Move it to be called by xe_gt_init_early(), so the locks and seqno are
initialized, avoiding a NULL ptr deref when wedging:

	xe 0000:03:00.0: [drm] *ERROR* GT0: load failed: status: Reset = 0, BootROM = 0x50, UKernel = 0x00, MIA = 0x00, Auth = 0x01
	xe 0000:03:00.0: [drm] *ERROR* GT0: firmware signature verification failed
	xe 0000:03:00.0: [drm] *ERROR* CRITICAL: Xe has declared device 0000:03:00.0 as wedged.
	...
	BUG: kernel NULL pointer dereference, address: 0000000000000000
	#PF: supervisor read access in kernel mode
	#PF: error_code(0x0000) - not-present page
	PGD 0 P4D 0
	Oops: Oops: 0000 [#1] PREEMPT SMP NOPTI
	CPU: 9 UID: 0 PID: 3908 Comm: modprobe Tainted: G     U  W          6.13.0-rc4-xe+ #3
	Tainted: [U]=USER, [W]=WARN
	Hardware name: Intel Corporation Alder Lake Client Platform/AlderLake-S ADP-S DDR5 UDIMM CRB, BIOS ADLSFWI1.R00.3275.A00.2207010640 07/01/2022
	RIP: 0010:xe_gt_tlb_invalidation_reset+0x75/0x110 [xe]

This can be easily triggered by poking the GuC binary to force a
signature failure. There will still be an extra message,

	xe 0000:03:00.0: [drm] *ERROR* GT0: GuC mmio request 0x4100: no reply 0x4100

but that's better than a NULL ptr deref.

Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3956
Fixes: c9474b726b93 ("drm/xe: Wedge the entire device")
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250103001111.331684-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
(cherry picked from commit 5001ef3af8f2c972d6fd9c5221a8457556f8bea6)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>xe/oa: Fix query mode of operation for OAR/OAC</title>
<updated>2025-01-02T18:01:21Z</updated>
<author>
<name>Umesh Nerlige Ramappa</name>
<email>umesh.nerlige.ramappa@intel.com</email>
</author>
<published>2024-12-20T17:19:18Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f0ed39830e6064d62f9c5393505677a26569bb56'/>
<id>urn:sha1:f0ed39830e6064d62f9c5393505677a26569bb56</id>
<content type='text'>
This is a set of squashed commits to facilitate smooth applying to
stable. Each commit message is retained for reference.

1) Allow a GGTT mapped batch to be submitted to user exec queue

For a OA use case, one of the HW registers needs to be modified by
submitting an MI_LOAD_REGISTER_IMM command to the users exec queue, so
that the register is modified in the user's hardware context. In order
to do this a batch that is mapped in GGTT, needs to be submitted to the
user exec queue. Since all user submissions use q-&gt;vm and hence PPGTT,
add some plumbing to enable submission of batches mapped in GGTT.

v2: ggtt is zero-initialized, so no need to set it false (Matt Brost)

2) xe/oa: Use MI_LOAD_REGISTER_IMMEDIATE to enable OAR/OAC

To enable OAR/OAC, a bit in RING_CONTEXT_CONTROL needs to be set.
Setting this bit cause the context image size to change and if not done
correct, can cause undesired hangs.

Current code uses a separate exec_queue to modify this bit and is
error-prone. As per HW recommendation, submit MI_LOAD_REGISTER_IMM to
the target hardware context to modify the relevant bit.

In v2 version, an attempt to submit everything to the user-queue was
made, but it failed the unprivileged-single-ctx-counters test. It
appears that the OACTXCONTROL must be modified from a remote context.

In v3 version, all context specific register configurations were moved
to use LOAD_REGISTER_IMMEDIATE and that seems to work well. This is a
cleaner way, since we can now submit all configuration to user
exec_queue and the fence handling is simplified.

v2:
(Matt)
- set job-&gt;ggtt to true if create job is successful
- unlock vm on job error

(Ashutosh)
- don't wait on job submission
- use kernel exec queue where possible

v3:
(Ashutosh)
- Fix checkpatch issues
- Remove extra spaces/new-lines
- Add Fixes: and Cc: tags
- Reset context control bit when OA stream is closed
- Submit all config via MI_LOAD_REGISTER_IMMEDIATE

(Umesh)
- Update commit message for v3 experiment
- Squash patches for easier port to stable

v4:
(Ashutosh)
- No need to pass q to xe_oa_submit_bb
- Do not support exec queues with width &gt; 1
- Fix disabling of CTX_CTRL_OAC_CONTEXT_ENABLE

v5:
(Ashutosh)
- Drop reg_lri related comments
- Use XE_OA_SUBMIT_NO_DEPS in xe_oa_load_with_lri

Fixes: 8135f1c09dd2 ("drm/xe/oa: Don't reset OAC_CONTEXT_ENABLE on OA stream close")
Signed-off-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt; # commit 1
Reviewed-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Cc: stable@vger.kernel.org
Reviewed-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241220171919.571528-2-umesh.nerlige.ramappa@intel.com
(cherry picked from commit 55039832f98c7e05f1cf9e0d8c12b2490abd0f16)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: Fix fault on fd close after unbind</title>
<updated>2024-12-23T15:19:52Z</updated>
<author>
<name>Lucas De Marchi</name>
<email>lucas.demarchi@intel.com</email>
</author>
<published>2024-12-18T05:31:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fe39b222a4139354d32ff9d46b88757f63f71d63'/>
<id>urn:sha1:fe39b222a4139354d32ff9d46b88757f63f71d63</id>
<content type='text'>
If userspace holds an fd open, unbinds the device and then closes it,
the driver shouldn't try to access the hardware. Protect it by using
drm_dev_enter()/drm_dev_exit(). This fixes the following page fault:

&lt;6&gt; [IGT] xe_wedged: exiting, ret=98
&lt;1&gt; BUG: unable to handle page fault for address: ffffc901bc5e508c
&lt;1&gt; #PF: supervisor read access in kernel mode
&lt;1&gt; #PF: error_code(0x0000) - not-present page
...
&lt;4&gt;   xe_lrc_update_timestamp+0x1c/0xd0 [xe]
&lt;4&gt;   xe_exec_queue_update_run_ticks+0x50/0xb0 [xe]
&lt;4&gt;   xe_exec_queue_fini+0x16/0xb0 [xe]
&lt;4&gt;   __guc_exec_queue_fini_async+0xc4/0x190 [xe]
&lt;4&gt;   guc_exec_queue_fini_async+0xa0/0xe0 [xe]
&lt;4&gt;   guc_exec_queue_fini+0x23/0x40 [xe]
&lt;4&gt;   xe_exec_queue_destroy+0xb3/0xf0 [xe]
&lt;4&gt;   xe_file_close+0xd4/0x1a0 [xe]
&lt;4&gt;   drm_file_free+0x210/0x280 [drm]
&lt;4&gt;   drm_close_helper.isra.0+0x6d/0x80 [drm]
&lt;4&gt;   drm_release_noglobal+0x20/0x90 [drm]

Fixes: 514447a12190 ("drm/xe: Stop accumulating LRC timestamp on job_free")
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3421
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241218053122.2730195-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
(cherry picked from commit 4ca1fd418338d4d135428a0eb1e16e3b3ce17ee8)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/pf: Use correct function to check LMEM provisioning</title>
<updated>2024-12-23T15:19:52Z</updated>
<author>
<name>Michal Wajdeczko</name>
<email>michal.wajdeczko@intel.com</email>
</author>
<published>2024-12-16T22:32:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=af12ba67d09ebe2b31ab997cea1a930864028562'/>
<id>urn:sha1:af12ba67d09ebe2b31ab997cea1a930864028562</id>
<content type='text'>
There is a typo in function call and instead of VF LMEM we were
looking at VF GGTT provisioning. Fix that.

Fixes: 234670cea9a2 ("drm/xe/pf: Skip fair VFs provisioning if already provisioned")
Signed-off-by: Michal Wajdeczko &lt;michal.wajdeczko@intel.com&gt;
Cc: Piotr Piórkowski &lt;piotr.piorkowski@intel.com&gt;
Reviewed-by: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241216223253.819-1-michal.wajdeczko@intel.com
(cherry picked from commit a8d0aa0e7fcd20c9f1992688c0f0d07a68287403)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
</feed>
