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<title>linux/drivers/gpu/host1x/dev.h, branch v4.20</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.20</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.20'/>
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<updated>2018-05-18T19:50:04Z</updated>
<entry>
<title>gpu: host1x: Remove wait check support</title>
<updated>2018-05-18T19:50:04Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2018-05-05T06:45:47Z</published>
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<id>urn:sha1:24c94e166dfe89839129b8e0fae208b6af60d6f1</id>
<content type='text'>
The job submission userspace ABI doesn't support this and there are no
plans to implement it, so all of this code is dead and can be removed.

Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Use IOMMU groups</title>
<updated>2017-12-21T13:52:36Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-11-14T15:11:28Z</published>
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<id>urn:sha1:41c3068cc2fd0ce179b910c4500934786e8156ba</id>
<content type='text'>
Use IOMMU groups to attach the host1x device to its IOMMU domain. This
is not strictly necessary because the domain isn't shared with any other
device, but it makes the code consistent with how IOMMU is handled in
other drivers and provides an easy way to detect when no IOMMU has been
attached via device tree.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Enable Tegra186 syncpoint protection</title>
<updated>2017-10-20T12:19:52Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-09-28T12:50:39Z</published>
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<id>urn:sha1:c3f52220f276504dea5615cc78750ddc9f468389</id>
<content type='text'>
Since Tegra186 the Host1x hardware allows syncpoints to be assigned to
specific channels, preventing any other channels from incrementing
them.

Enable this feature where available and assign syncpoints to channels
when submitting a job. Syncpoints are currently never unassigned from
channels since that would require extra work and is unnecessary with
the current channel allocation model.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add Tegra186 support</title>
<updated>2017-10-20T12:19:51Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-09-05T08:43:05Z</published>
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<id>urn:sha1:f1b53c4e2c08cbd805a2fdede0026edb30b59602</id>
<content type='text'>
Add support for the implementation of Host1x present on the Tegra186.
The register space has been shuffled around a little bit, requiring
addition of some chip-specific code sections. Tegra186 also adds
several new features, most importantly the hypervisor, but those are
not yet supported with this commit.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Refactor channel allocation code</title>
<updated>2017-06-15T12:25:38Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2017-06-14T23:18:42Z</published>
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<id>urn:sha1:8474b02531c4881a762c52ef869c52429e38633f</id>
<content type='text'>
This is largely a rewrite of the Host1x channel allocation code, bringing
several changes:

- The previous code could deadlock due to an interaction
  between the 'reflock' mutex and CDMA timeout handling.
  This gets rid of the mutex.
- Support for more than 32 channels, required for Tegra186
- General refactoring, including better encapsulation
  of channel ownership handling into channel.c

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Support module reset</title>
<updated>2017-04-05T16:11:50Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-03-21T07:54:22Z</published>
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<id>urn:sha1:b386c6b73ac6c2a9a2f1201d055ab65cc19890a2</id>
<content type='text'>
Newer versions of Tegra come with early boot software that aggressively
puts various modules in reset. Add support to the host1x driver to take
the module out of reset on probe, and assert reset on removal.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Sort includes alphabetically</title>
<updated>2017-04-05T16:11:49Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-03-21T07:54:21Z</published>
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<id>urn:sha1:7e7d432c5a736e7106c8700b65d8c31b93bd1c82</id>
<content type='text'>
Sorting includes alphabetically makes it easier and less conflict-prone
to add new includes subsequently.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add IOMMU support</title>
<updated>2017-04-05T16:11:43Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2016-12-14T11:16:14Z</published>
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<id>urn:sha1:404bfb78daf3bedafb0bfab24947059575cbea3d</id>
<content type='text'>
Add support for the Host1x unit to be located behind
an IOMMU. This is required when gather buffers may be
allocated non-contiguously in physical memory, as can
be the case when TegraDRM is also using the IOMMU.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add locking to syncpt</title>
<updated>2016-11-11T14:33:13Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2016-11-08T17:51:33Z</published>
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<id>urn:sha1:d4b5781890b9329b9e7720f14d3eeb5661348535</id>
<content type='text'>
Currently syncpoints are not locked by mutex and this causes races
if we are aggressively freeing and allocating syncpoints.

This patch adds missing mutex protection to syncpoint structures.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Reviewed-by: Shridhar Rasal &lt;srasal@nvidia.com&gt;
Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
[treding@nvidia.com: use better label names, don't reset local variable]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Use unsigned int consistently for IDs</title>
<updated>2016-06-23T09:59:24Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-23T09:19:00Z</published>
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<id>urn:sha1:5c0d8d386ba67ce07bfddcebf05233e8606771ff</id>
<content type='text'>
IDs can never be negative so use unsigned int. In some instances an
explicitly sized type (such as u32) was used for no particular reason,
so turn those into unsigned int as well for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
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