<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/host1x/dev.h, branch v4.5</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.5</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.5'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-03-04T15:24:56Z</updated>
<entry>
<title>gpu: host1x: Set DMA mask</title>
<updated>2016-03-04T15:24:56Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-02-26T09:06:52Z</published>
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<id>urn:sha1:097452e61366a939a4772332181cea7cdcc74760</id>
<content type='text'>
The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add MIPI pad calibration support</title>
<updated>2013-12-19T08:29:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-09-02T07:48:53Z</published>
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<id>urn:sha1:4de6a2d6acb0e2a840f07db17def7e674b9d2bb4</id>
<content type='text'>
This driver adds support to perform calibration of the MIPI pads for CSI
and DSI.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add syncpoint base support</title>
<updated>2013-10-31T08:55:48Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2013-10-14T12:21:53Z</published>
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<id>urn:sha1:f5a954fed9b3eb04973ede72c50c66157fa9e15b</id>
<content type='text'>
This patch adds support for hardware syncpoint bases. This creates
a simple mechanism to stall the command FIFO until an operation is
completed.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Reviewed-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Move subdevice infrastructure to host1x</title>
<updated>2013-10-31T08:55:33Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-10-14T12:43:22Z</published>
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<id>urn:sha1:776dc38403676f499a73d32e2e7c61eb5b42f736</id>
<content type='text'>
The Tegra DRM driver currently uses some infrastructure to defer the DRM
core initialization until all required devices have registered. The same
infrastructure can potentially be used by any other driver that requires
more than a single sub-device of the host1x module.

Make the infrastructure more generic and keep only the DRM specific code
in the DRM part of the driver. Eventually this will make it easy to move
the DRM driver part back to the DRM subsystem.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Sort drivers by probe order</title>
<updated>2013-09-03T08:10:12Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-09-03T07:02:22Z</published>
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<id>urn:sha1:57c6eb6f2cf89baef4188b4257b3e756f9aebef4</id>
<content type='text'>
External driver declarations are sorted by probe order for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Rework CPU syncpoint increment</title>
<updated>2013-06-22T10:43:55Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2013-05-29T10:26:08Z</published>
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<id>urn:sha1:ebae30b1fbcc2cc991ce705cc82e16d1e5ddbf51</id>
<content type='text'>
This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as
they are in practise doing the same thing. host1x_syncpt_incr() is
also modified to return error codes. User space interface is modified
accordingly to pass return values.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Acked-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Remove second host1x driver</title>
<updated>2013-04-22T10:39:59Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:07Z</published>
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<id>urn:sha1:692e6d7be8099225f04b2d97299bc03479a5fcdb</id>
<content type='text'>
Remove second host1x driver, and bind tegra-drm to the new host1x
driver. The logic to parse device tree and track clients is moved
to drm.c.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add debug support</title>
<updated>2013-04-22T10:32:46Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:04Z</published>
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<id>urn:sha1:6236451d83a720072053855fa63d51934024a707</id>
<content type='text'>
Add support for host1x debugging. Adds debugfs entries, and dumps
channel state to UART in case of stuck job.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add channel support</title>
<updated>2013-04-22T10:32:43Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:03Z</published>
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<id>urn:sha1:6579324a41cc414009a601738b70a53d6376325c</id>
<content type='text'>
Add support for host1x client modules, and host1x channels to submit
work to the clients.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add syncpoint wait and interrupts</title>
<updated>2013-04-22T10:32:42Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:02Z</published>
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<id>urn:sha1:7ede0b0bf3e2595d40d6195b6fe4c4dcef438830</id>
<content type='text'>
Add support for sync point interrupts, and sync point wait. Sync
point wait used interrupts for unblocking wait.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
</feed>
