<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/host1x/dev.h, branch v4.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.9'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-06-23T09:59:24Z</updated>
<entry>
<title>gpu: host1x: Use unsigned int consistently for IDs</title>
<updated>2016-06-23T09:59:24Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-23T09:19:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5c0d8d386ba67ce07bfddcebf05233e8606771ff'/>
<id>urn:sha1:5c0d8d386ba67ce07bfddcebf05233e8606771ff</id>
<content type='text'>
IDs can never be negative so use unsigned int. In some instances an
explicitly sized type (such as u32) was used for no particular reason,
so turn those into unsigned int as well for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Consistently use unsigned int for counts</title>
<updated>2016-06-23T09:59:23Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2016-06-22T14:44:07Z</published>
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<id>urn:sha1:14c95fc896e1d3929abde448fd86c07bdbae56d5</id>
<content type='text'>
The number of channels, syncpoints, bases and mlocks can never be
negative, so use unsigned int instead of int. Also make loop variables
the same type for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: hw: intr_hw: Remove create_workqueue</title>
<updated>2016-06-23T09:59:22Z</updated>
<author>
<name>Bhaktipriya Shridhar</name>
<email>bhaktipriya96@gmail.com</email>
</author>
<published>2016-06-18T09:06:32Z</published>
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<id>urn:sha1:57574bd779852bb7328ade70c951b681b54a7ece</id>
<content type='text'>
System workqueues have been able to handle high level of concurrency
for a long time now and there's no reason to use dedicated workqueues
just to gain concurrency. Since the workqueue host-&gt;intr_wq is involved
in sync point interrupts, and sync point wait and is not being used on
a memory reclaim path, dedicated host-&gt;intr_wq has been replaced with the
use of system_wq.

Unlike a dedicated per-cpu workqueue created with create_workqueue(),
system_wq allows multiple work items to overlap executions even on
the same CPU; however, a per-cpu workqueue doesn't have any CPU
locality or global ordering guarantees unless the target CPU is
explicitly specified and thus the increase of local concurrency
shouldn't make any difference.

cancel_work_sync() has been used  in _host1x_free_syncpt_irq() to ensure
that no work is pending by the time exit path runs.

Signed-off-by: Bhaktipriya Shridhar &lt;bhaktipriya96@gmail.com&gt;
Acked-by: Tejun Heo &lt;tj@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Set DMA mask</title>
<updated>2016-03-04T15:24:56Z</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2016-02-26T09:06:52Z</published>
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<id>urn:sha1:097452e61366a939a4772332181cea7cdcc74760</id>
<content type='text'>
The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.

Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add MIPI pad calibration support</title>
<updated>2013-12-19T08:29:43Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-09-02T07:48:53Z</published>
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<id>urn:sha1:4de6a2d6acb0e2a840f07db17def7e674b9d2bb4</id>
<content type='text'>
This driver adds support to perform calibration of the MIPI pads for CSI
and DSI.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add syncpoint base support</title>
<updated>2013-10-31T08:55:48Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2013-10-14T12:21:53Z</published>
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<id>urn:sha1:f5a954fed9b3eb04973ede72c50c66157fa9e15b</id>
<content type='text'>
This patch adds support for hardware syncpoint bases. This creates
a simple mechanism to stall the command FIFO until an operation is
completed.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Reviewed-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Move subdevice infrastructure to host1x</title>
<updated>2013-10-31T08:55:33Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-10-14T12:43:22Z</published>
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<id>urn:sha1:776dc38403676f499a73d32e2e7c61eb5b42f736</id>
<content type='text'>
The Tegra DRM driver currently uses some infrastructure to defer the DRM
core initialization until all required devices have registered. The same
infrastructure can potentially be used by any other driver that requires
more than a single sub-device of the host1x module.

Make the infrastructure more generic and keep only the DRM specific code
in the DRM part of the driver. Eventually this will make it easy to move
the DRM driver part back to the DRM subsystem.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Sort drivers by probe order</title>
<updated>2013-09-03T08:10:12Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2013-09-03T07:02:22Z</published>
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<id>urn:sha1:57c6eb6f2cf89baef4188b4257b3e756f9aebef4</id>
<content type='text'>
External driver declarations are sorted by probe order for consistency.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Rework CPU syncpoint increment</title>
<updated>2013-06-22T10:43:55Z</updated>
<author>
<name>Arto Merilainen</name>
<email>amerilainen@nvidia.com</email>
</author>
<published>2013-05-29T10:26:08Z</published>
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<id>urn:sha1:ebae30b1fbcc2cc991ce705cc82e16d1e5ddbf51</id>
<content type='text'>
This patch merges host1x_syncpt_cpu_incr to host1x_syncpt_incr() as
they are in practise doing the same thing. host1x_syncpt_incr() is
also modified to return error codes. User space interface is modified
accordingly to pass return values.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Acked-By: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@gmail.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Remove second host1x driver</title>
<updated>2013-04-22T10:39:59Z</updated>
<author>
<name>Terje Bergstrom</name>
<email>tbergstrom@nvidia.com</email>
</author>
<published>2013-03-22T14:34:07Z</published>
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<id>urn:sha1:692e6d7be8099225f04b2d97299bc03479a5fcdb</id>
<content type='text'>
Remove second host1x driver, and bind tegra-drm to the new host1x
driver. The logic to parse device tree and track clients is moved
to drm.c.

Signed-off-by: Arto Merilainen &lt;amerilainen@nvidia.com&gt;
Signed-off-by: Terje Bergstrom &lt;tbergstrom@nvidia.com&gt;
Reviewed-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
Tested-by: Erik Faye-Lund &lt;kusmabite@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;thierry.reding@avionic-design.de&gt;
</content>
</entry>
</feed>
