linux/drivers/gpu/host1x/dev.h, branch v5.8

gpu: host1x: Set DMA mask based on IOMMU setup

2019-10-29T14:04:35Z

If the Tegra DRM clients are backed by an IOMMU, push buffers are likely to be allocated beyond the 32-bit boundary if sufficient system memory is available. This is problematic on earlier generations of Tegra where host1x supports a maximum of 32 address bits for the GATHER opcode. More recent versions of Tegra (Tegra186 and later) have a wide variant of the GATHER opcode, which allows addressing up to 64 bits of memory. If host1x itself is behind an IOMMU as well this doesn't matter because the IOMMU's input address space is restricted to 32 bits on generations without support for wide GATHER opcodes. However, if host1x is not behind an IOMMU, it won't be able to process push buffers beyond the 32-bit boundary on Tegra generations that don't support wide GATHER opcodes. Restrict the DMA mask to 32 bits on these generations prevents buffers from being allocated from beyond the 32-bit boundary. Signed-off-by: Thierry Reding

gpu: host1x: Do not limit DMA segment size

2019-10-28T10:18:08Z

host1x nor any its clients have any limitations on the DMA segment size, so don't pretend that they do. Signed-off-by: Thierry Reding

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30T18:29:52Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Steve Winslow Reviewed-by: Richard Fontana Reviewed-by: Alexios Zavras Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman

gpu: host1x: Set up stream ID table

2019-02-04T07:35:55Z

In order to enable the MMIO path stream ID protection provided by the incarnation of host1x found in Tegra186 and later, the host1x must be provided with the list of stream ID register offsets for each of its clients. Some clients (such as VIC) have multiple stream ID registers that are assumed to be contiguous. The host1x is programmed with the base offset and a limit which provide the range of registers that the host1x needs to monitor for writes. Signed-off-by: Thierry Reding

gpu: host1x: Remove wait check support

2018-05-18T19:50:04Z

The job submission userspace ABI doesn't support this and there are no plans to implement it, so all of this code is dead and can be removed. Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: Use IOMMU groups

2017-12-21T13:52:36Z

Use IOMMU groups to attach the host1x device to its IOMMU domain. This is not strictly necessary because the domain isn't shared with any other device, but it makes the code consistent with how IOMMU is handled in other drivers and provides an easy way to detect when no IOMMU has been attached via device tree. Signed-off-by: Thierry Reding

gpu: host1x: Enable Tegra186 syncpoint protection

2017-10-20T12:19:52Z

Since Tegra186 the Host1x hardware allows syncpoints to be assigned to specific channels, preventing any other channels from incrementing them. Enable this feature where available and assign syncpoints to channels when submitting a job. Syncpoints are currently never unassigned from channels since that would require extra work and is unnecessary with the current channel allocation model. Signed-off-by: Mikko Perttunen Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: Add Tegra186 support

2017-10-20T12:19:51Z

Add support for the implementation of Host1x present on the Tegra186. The register space has been shuffled around a little bit, requiring addition of some chip-specific code sections. Tegra186 also adds several new features, most importantly the hypervisor, but those are not yet supported with this commit. Signed-off-by: Mikko Perttunen Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: Refactor channel allocation code

2017-06-15T12:25:38Z

This is largely a rewrite of the Host1x channel allocation code, bringing several changes: - The previous code could deadlock due to an interaction between the 'reflock' mutex and CDMA timeout handling. This gets rid of the mutex. - Support for more than 32 channels, required for Tegra186 - General refactoring, including better encapsulation of channel ownership handling into channel.c Signed-off-by: Mikko Perttunen Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: Support module reset

2017-04-05T16:11:50Z

Newer versions of Tegra come with early boot software that aggressively puts various modules in reset. Add support to the host1x driver to take the module out of reset on probe, and assert reset on removal. Signed-off-by: Thierry Reding