<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/host1x, branch v3.19</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v3.19</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v3.19'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2014-11-13T15:11:57Z</updated>
<entry>
<title>gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register</title>
<updated>2014-11-13T15:11:57Z</updated>
<author>
<name>Sean Paul</name>
<email>seanpaul@chromium.org</email>
</author>
<published>2014-09-10T14:52:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b298e98ef6ab9c4279b427db717a1624ef722751'/>
<id>urn:sha1:b298e98ef6ab9c4279b427db717a1624ef722751</id>
<content type='text'>
During calibration, sets the "internal reference level for drive pull-
down" to the value specified in the Tegra TRM.

Signed-off-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Calibrate clock lanes</title>
<updated>2014-11-13T15:11:54Z</updated>
<author>
<name>Sean Paul</name>
<email>seanpaul@chromium.org</email>
</author>
<published>2014-09-10T14:52:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=08a15cc34ddf7b7247122de44687364bcd82c2bf'/>
<id>urn:sha1:08a15cc34ddf7b7247122de44687364bcd82c2bf</id>
<content type='text'>
Include the clock lanes when calibrating the MIPI PHY on Tegra124
compatible devices.

Signed-off-by: Sean Paul &lt;seanpaul@chromium.org&gt;
[treding@nvidia.com: bikeshedding]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL</title>
<updated>2014-11-13T15:11:51Z</updated>
<author>
<name>Sean Paul</name>
<email>seanpaul@chromium.org</email>
</author>
<published>2014-09-10T14:52:03Z</published>
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<id>urn:sha1:26f7a92a3a275cad7b0f39063e8cd92e002aff1a</id>
<content type='text'>
By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE
("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the
description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states
that if the value of the prescale is 0 (or 0.1us), the filter should be
set between 2-5. However, the current code sets it to 0.

For now, let's keep the prescale and filter values as-is, which is most
likely the power-on-reset values of 0x2 and 0xa, respectively.

Signed-off-by: Sean Paul &lt;seanpaul@chromium.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: mipi: Registers are 32 bits wide</title>
<updated>2014-11-13T15:11:48Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-10-02T12:33:31Z</published>
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<id>urn:sha1:57b17ae71f412b870415b698655f00846e34ce0a</id>
<content type='text'>
On 64-bit platforms an unsigned long would be 64 bit and cause
unnecessary casting when being passed to writel() or returned from
readl(). Make register values 32 bits wide to avoid that.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Make gather offsets unsigned</title>
<updated>2014-11-13T15:11:44Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-12T11:26:19Z</published>
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<id>urn:sha1:3880e95f2706e4ad9ba37e382e7f5bb82f911c68</id>
<content type='text'>
Use the u32 type for the offset in the host1x_job_gather structure for
consistentcy with other structures. Negative offsets don't make sense in
this context.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Print address/offset pairs consistently</title>
<updated>2014-11-13T15:11:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-12T11:24:17Z</published>
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<id>urn:sha1:ba73fbc2ca221e80c6733e68496ad07bc3b58ff8</id>
<content type='text'>
Consistently use a format of %pad+%#x to print address/offset in debug
messages.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix typo in comment</title>
<updated>2014-11-13T15:11:38Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-12T11:17:48Z</published>
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<id>urn:sha1:7f27d60b28f6dbc9762407aac596b53f2a71a867</id>
<content type='text'>
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Make mapped field of push buffers void *</title>
<updated>2014-11-13T15:11:35Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-12T11:16:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0169b93f4492c74d046b456d93b37bd7b55ecd42'/>
<id>urn:sha1:0169b93f4492c74d046b456d93b37bd7b55ecd42</id>
<content type='text'>
This reduces the amount of casting that needs to be done to get rid of
annoying warnings on 64-bit builds.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Use struct host1x_bo pointers in traces</title>
<updated>2014-11-13T15:11:32Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-12T11:14:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b40d02bf96e05851d1d16b4a75f66a9e16cfb2fb'/>
<id>urn:sha1:b40d02bf96e05851d1d16b4a75f66a9e16cfb2fb</id>
<content type='text'>
Rather than cast to a u32 use the struct host1x_bo pointers directly.
This avoid annoying warnings for 64-bit builds.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Make job submission 64-bit safe</title>
<updated>2014-08-04T08:07:36Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-06-10T08:25:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=961e3beae3b29ae9463631415342244cdaf1cd47'/>
<id>urn:sha1:961e3beae3b29ae9463631415342244cdaf1cd47</id>
<content type='text'>
Job submission currently relies on the fact that struct drm_tegra_reloc
and struct host1x_reloc are the same size and uses a simple call to the
copy_from_user() function to copy them to kernel space. This causes the
handle to be stored in the buffer object field, which then needs a cast
to a 32 bit integer to resolve it to a proper buffer object pointer and
store it back in the buffer object field.

On 64-bit architectures that will no longer work, since pointers are 64
bits wide whereas handles will remain 32 bits. This causes the sizes of
both structures to because different and copying will no longer work.

Fix this by adding a new function, host1x_reloc_get_user(), that copies
the structures field by field.

While at it, use substructures for the command and target buffers in
struct host1x_reloc for better readability. Also use unsized types to
make it more obvious that this isn't part of userspace ABI.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
