linux/drivers/gpu/host1x, branch v5.12

gpu: host1x: Use different lock classes for each client

2021-03-30T17:37:20Z

To avoid false lockdep warnings, give each client lock a different lock class, passed from the initialization site by macro. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu/host1x: bus: Add missing description for 'driver'

2020-11-05T21:12:55Z

Fixes the following W=1 kernel build warning(s): drivers/gpu/host1x/bus.c:40: warning: Function parameter or member 'driver' not described in 'host1x_subdev_add' Cc: Thierry Reding Cc: dri-devel@lists.freedesktop.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones Acked-by: Thierry Reding Signed-off-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20201105144517.1826692-2-lee.jones@linaro.org

Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm

2020-10-15T17:46:16Z

Pull drm updates from Dave Airlie: "Not a major amount of change, the i915 trees got split into display and gt trees to better facilitate higher level review, and there's a major refactoring of i915 GEM locking to use more core kernel concepts (like ww-mutexes). msm gets per-process pagetables, older AMD SI cards get DC support, nouveau got a bump in displayport support with common code extraction from i915. Outside of drm this contains a couple of patches for hexint moduleparams which you've acked, and a virtio common code tree that you should also get via it's regular path. New driver: - Cadence MHDP8546 DisplayPort bridge driver core: - cross-driver scatterlist cleanups - devm_drm conversions - remove drm_dev_init - devm_drm_dev_alloc conversion ttm: - lots of refactoring and cleanups bridges: - chained bridge support in more drivers panel: - misc new panels scheduler: - cleanup priority levels displayport: - refactor i915 code into helpers for nouveau i915: - split into display and GT trees - WW locking refactoring in GEM - execbuf2 extension mechanism - syncobj timeline support - GEN 12 HOBL display powersaving - Rocket Lake display additions - Disable FBC on Tigerlake - Tigerlake Type-C + DP improvements - Hotplug interrupt refactoring amdgpu: - Sienna Cichlid updates - Navy Flounder updates - DCE6 (SI) support for DC - Plane rotation enabled - TMZ state info ioctl - PCIe DPC recovery support - DC interrupt handling refactor - OLED panel fixes amdkfd: - add SMI events for thermal throttling - SMI interface events ioctl update - process eviction counters radeon: - move to dma_ for allocations - expose sclk via sysfs msm: - DSI support for sm8150/sm8250 - per-process GPU pagetable support - Displayport support mediatek: - move HDMI phy driver to PHY - convert mtk-dpi to bridge API - disable mt2701 tmds tegra: - bridge support exynos: - misc cleanups vc4: - dual display cleanups ast: - cleanups gma500: - conversion to GPIOd API hisilicon: - misc reworks ingenic: - clock handling and format improvements mcde: - DSI support mgag200: - desktop g200 support mxsfb: - i.MX7 + i.MX8M - alpha plane support panfrost: - devfreq support - amlogic SoC support ps8640: - EDID from eDP retrieval tidss: - AM65xx YUV workaround virtio: - virtio-gpu exported resources rcar-du: - R8A7742, R8A774E1 and R8A77961 support - YUV planar format fixes - non-visible plane handling - VSP device reference count fix - Kconfig fix to avoid displaying disabled options in .config" * tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm: (1494 commits) drm/ingenic: Fix bad revert drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init drm/amdgpu: Remove warning for virtual_display drm/amdgpu: kfd_initialized can be static drm/amd/pm: setup APU dpm clock table in SMU HW initialization drm/amdgpu: prevent spurious warning drm/amdgpu/swsmu: fix ARC build errors drm/amd/display: Fix OPTC_DATA_FORMAT programming drm/amd/display: Don't allow pstate if no support in blank drm/panfrost: increase readl_relaxed_poll_timeout values MAINTAINERS: Update entry for st7703 driver after the rename Revert "gpu/drm: ingenic: Add option to mmap GEM buffers cached" drm/amd/display: HDMI remote sink need mode validation for Linux drm/amd/display: Change to correct unit on audio rate drm/amd/display: Avoid set zero in the requested clk drm/amdgpu: align frag_end to covered address space drm/amdgpu: fix NULL pointer dereference for Renoir drm/vmwgfx: fix regression in thp code due to ttm init refactor. drm/amdgpu/swsmu: add interrupt work handler for smu11 parts drm/amdgpu/swsmu: add interrupt work function ...

drm: host1x: fix common struct sg_table related issues

2020-09-10T06:18:35Z

The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function returns the number of the created entries in the DMA address space. However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and dma_unmap_sg must be called with the original number of the entries passed to the dma_map_sg(). struct sg_table is a common structure used for describing a non-contiguous memory buffer, used commonly in the DRM and graphics subsystems. It consists of a scatterlist with memory pages and DMA addresses (sgl entry), as well as the number of scatterlist entries: CPU pages (orig_nents entry) and DMA mapped pages (nents entry). It turned out that it was a common mistake to misuse nents and orig_nents entries, calling DMA-mapping functions with a wrong number of entries or ignoring the number of mapped entries returned by the dma_map_sg() function. To avoid such issues, lets use a common dma-mapping wrappers operating directly on the struct sg_table objects and use scatterlist page iterators where possible. This, almost always, hides references to the nents and orig_nents entries, making the code robust, easier to follow and copy/paste safe. Signed-off-by: Marek Szyprowski Reviewed-by: Robin Murphy

media: gpu: host1x: mipi: Keep MIPI clock enabled and mutex locked till calibration done

2020-08-28T13:12:38Z

With the split of MIPI calibration into tegra_mipi_calibrate() and tegra_mipi_wait(), MIPI clock is not kept enabled and mutex is not locked till the calibration is done. So, this patch keeps MIPI clock enabled and mutex locked after triggering start of calibration till its done. To let calibration process go through its finite sequence codes before calibration logic waiting for pads idle state added wait time of 75usec to make sure it sees idle state to apply the results. This patch renames tegra_mipi_calibrate() as tegra_mipi_start_calibration() and tegra_mipi_wait() as tegra_mipi_finish_calibration() to be inline with their usage. Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

gpu: host1x: debug: Dump push buffer state

2020-07-17T14:06:14Z

When job hangs and there is a memory error pointing at channel's push buffer, it is very handy to know the push buffer's state. This patch makes the push buffer's state to be dumped into KMSG in addition to the job's gathers. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: debug: Fix multiple channels emitting messages simultaneously

2020-07-17T14:06:14Z

Once channel's job is hung, it dumps the channel's state into KMSG before tearing down the offending job. If multiple channels hang at once, then they dump messages simultaneously, making the debug info unreadable, and thus, useless. This patch adds mutex which allows only one channel to emit debug messages at a time. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: Put gather's BO on pinning error

2020-07-17T14:06:14Z

This patch fixes gather's BO refcounting on a pinning error. Gather's BO won't be leaked now if something goes wrong. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: Optimize BOs usage when firewall is enabled

2020-07-17T14:06:14Z

We don't need to hold and pin original BOs of the gathers in a case of enabled firewall because in this case gather's content is copied and the copy is used by the executed job. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

gpu: host1x: mipi: Split tegra_mipi_calibrate() and tegra_mipi_wait()

2020-07-17T14:06:14Z

SW can trigger MIPI pads calibration any time after power on but calibration results will be latched and applied to the pads by MIPI CAL unit only when the link is in LP-11 state and then status register will be updated. For CSI, trigger of pads calibration happen during CSI stream enable where CSI receiver is kept ready prior to sensor or CSI transmitter stream start. So, pads may not be in LP-11 at this time and waiting for the calibration to be done immediate after calibration start will result in timeout. This patch splits tegra_mipi_calibrate() and tegra_mipi_wait() so triggering for calibration and waiting for it to complete can happen at different stages. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding