<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/gpu/host1x, branch v5.17</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.17</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.17'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2022-02-16T16:20:53Z</updated>
<entry>
<title>gpu: host1x: Always return syncpoint value when waiting</title>
<updated>2022-02-16T16:20:53Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-02-07T13:19:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=184b58fa816fb5ee1854daf0d430766422bf2a77'/>
<id>urn:sha1:184b58fa816fb5ee1854daf0d430766422bf2a77</id>
<content type='text'>
The new TegraDRM UAPI uses syncpoint waiting with timeout set to
zero to indicate reading the syncpoint value. To support that we
need to return the syncpoint value always when waiting.

Fixes: 44e961381354 ("drm/tegra: Implement syncpoint wait UAPI")
Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Fix hang on Tegra186+</title>
<updated>2022-01-27T17:27:02Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-12-23T14:46:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=22d7ee32f1fb6d51ef8cf657c6685ca04745755a'/>
<id>urn:sha1:22d7ee32f1fb6d51ef8cf657c6685ca04745755a</id>
<content type='text'>
Tegra186+ hangs if host1x hardware is disabled at a kernel boot time
because we touch hardware before runtime PM is resumed. Move sync point
assignment initialization to the RPM-resume callback. Older SoCs were
unaffected because they skip that sync point initialization.

Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt; # T186
Reported-by: Jon Hunter &lt;jonathanh@nvidia.com&gt; # T186
Fixes: 6b6776e2ab8a ("gpu: host1x: Add initial runtime PM and OPP support")
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add back arm_iommu_detach_device()</title>
<updated>2021-12-16T13:28:51Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-12-04T14:58:48Z</published>
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<id>urn:sha1:d5185965c3b59073c4520bad7dd2adf725b9abba</id>
<content type='text'>
Host1x DMA buffer isn't mapped properly when CONFIG_ARM_DMA_USE_IOMMU=y.
The memory management code of Host1x driver has a longstanding overhaul
overdue and it's not obvious where the problem is in this case. Hence
let's add back the old workaround which we already had sometime before.
It explicitly detaches Host1x device from the offending implicit IOMMU
domain. This fixes a completely broken Host1x DMA in case of ARM32
multiplatform kernel config.

Cc: stable@vger.kernel.org
Fixes: af1cbfb9bf0f ("gpu: host1x: Support DMA mapping of buffers")
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add host1x_channel_stop()</title>
<updated>2021-12-16T13:07:07Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:16Z</published>
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<id>urn:sha1:9ca790f44606109071ab1a3a37ed99e91794c37c</id>
<content type='text'>
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before client enters into suspend.

Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt; # Ouya T30
Tested-by: Paul Fertser &lt;fercerpav@gmail.com&gt; # PAZ00 T20
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt; # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar &lt;mattmerhar@protonmail.com&gt; # Ouya T30
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add initial runtime PM and OPP support</title>
<updated>2021-12-16T13:07:07Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:15Z</published>
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<id>urn:sha1:6b6776e2ab8ac7086cf31ad339411df7681715b7</id>
<content type='text'>
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handling and we're going to remove some of these paths in the future.

Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt; # Ouya T30
Tested-by: Paul Fertser &lt;fercerpav@gmail.com&gt; # PAZ00 T20
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt; # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar &lt;mattmerhar@protonmail.com&gt; # Ouya T30
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Add missing DMA API include</title>
<updated>2021-12-16T13:07:07Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2021-12-10T17:54:43Z</published>
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<id>urn:sha1:4abfc0e3a5460499ce1062cf94089490aade7ca4</id>
<content type='text'>
Host1x seems to be relying on picking up dma-mapping.h transitively from
iova.h, which has no reason to include it in the first place. Fix the
former issue before we totally break things by fixing the latter one.

CC: Thierry Reding &lt;thierry.reding@gmail.com&gt;
CC: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
CC: dri-devel@lists.freedesktop.org
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: select CONFIG_DMA_SHARED_BUFFER</title>
<updated>2021-12-16T13:07:06Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2021-09-27T09:36:59Z</published>
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<id>urn:sha1:6c7a388b62366f0de9936db3c1921d7f4e0011bc</id>
<content type='text'>
Linking fails when dma-buf is disabled:

ld.lld: error: undefined symbol: dma_fence_release
&gt;&gt;&gt; referenced by fence.c
&gt;&gt;&gt;               gpu/host1x/fence.o:(host1x_syncpt_fence_enable_signaling) in archive drivers/built-in.a
&gt;&gt;&gt; referenced by fence.c
&gt;&gt;&gt;               gpu/host1x/fence.o:(host1x_fence_signal) in archive drivers/built-in.a
&gt;&gt;&gt; referenced by fence.c
&gt;&gt;&gt;               gpu/host1x/fence.o:(do_fence_timeout) in archive drivers/built-in.a

Fixes: 687db2207b1b ("gpu: host1x: Add DMA fence implementation")
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Drop excess kernel-doc entry @key</title>
<updated>2021-12-16T13:07:06Z</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2021-10-05T05:37:26Z</published>
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<id>urn:sha1:ab3c971d2fd33f49a5c99c30cde8f50bb2b541d3</id>
<content type='text'>
Fix kernel-doc warning in host1x:

../drivers/gpu/host1x/bus.c:774: warning: Excess function parameter 'key' description in '__host1x_client_register'

Fixes: 0cfe5a6e758f ("gpu: host1x: Split up client initalization and registration")
Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Thierry Reding &lt;thierry.reding@gmail.com&gt;
Cc: dri-devel@lists.freedesktop.org
Cc: linux-tegra@vger.kernel.org
Cc: David Airlie &lt;airlied@linux.ie&gt;
Cc: Daniel Vetter &lt;daniel@ffwll.ch&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Add NVDEC driver</title>
<updated>2021-12-16T13:07:06Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2021-09-16T14:55:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=46f226c93d35b936aeec6eb31da932dc2e86f413'/>
<id>urn:sha1:46f226c93d35b936aeec6eb31da932dc2e86f413</id>
<content type='text'>
Add support for booting and using NVDEC on Tegra210, Tegra186
and Tegra194 to the Host1x and TegraDRM drivers. Booting in
secure mode is not currently supported.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Implement buffer object cache</title>
<updated>2021-12-16T13:07:06Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-02-07T15:50:52Z</published>
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<id>urn:sha1:1f39b1dfa53c84b56d7ad37fed44afda7004959d</id>
<content type='text'>
This cache is used to avoid mapping and unmapping buffer objects
unnecessarily. Mappings are cached per client and stay hot until
the buffer object is destroyed.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
