linux/drivers/gpu/host1x, branch v6.2

gpu: host1x: Staticize host1x_syncpt_fence_ops

2022-11-25T15:14:59Z

This structure is never used outside the file, so make it locally scoped. Signed-off-by: Thierry Reding

gpu: host1x: Use DEFINE_SHOW_ATTRIBUTE to simplify debugfs code

2022-11-25T15:14:59Z

Use DEFINE_SHOW_ATTRIBUTE helper macro to simplify the debugfs code for the status and status_all entries. No functional change. Signed-off-by: Liu Shixin Signed-off-by: Thierry Reding

gpu: host1x: Add stream ID register data for NVDEC on Tegra234

2022-11-25T15:14:58Z

Add entries for NVDEC to the Tegra234 SID table. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Select context device based on attached IOMMU

2022-11-25T15:14:19Z

On Tegra234, engines that are programmed through Host1x channels can be attached to either the NISO0 or NISO1 SMMU. Because of that, when selecting a context device to use with an engine, we need to select one that is also attached to the same SMMU. Add a parameter to host1x_memory_context_alloc to specify which device we are allocating a context for, and use it to pick an appropriate context device. Signed-off-by: Mikko Perttunen [treding@nvidia.com: update !IOMMU_API stub signature] Signed-off-by: Thierry Reding

gpu: host1x: Avoid trying to use GART on Tegra20

2022-11-18T08:33:20Z

Since commit c7e3ca515e78 ("iommu/tegra: gart: Do not register with bus") quite some time ago, the GART driver has effectively disabled itself to avoid issues with the GPU driver expecting it to work in ways that it doesn't. As of commit 57365a04c921 ("iommu: Move bus setup to IOMMU device registration") that bodge no longer works, but really the GPU driver should be responsible for its own behaviour anyway. Make the workaround explicit. Reported-by: Jon Hunter Suggested-by: Dmitry Osipenko Signed-off-by: Robin Murphy Tested-by: Jon Hunter Signed-off-by: Thierry Reding

gpu: host1x: Use the bitmap API to allocate bitmaps

2022-07-08T15:38:34Z

Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. While at it, remove a useless bitmap_zero() call. The bitmap is already zero'ed when allocated. Signed-off-by: Christophe JAILLET Signed-off-by: Thierry Reding

gpu: host1x: Generalize host1x_cdma_push_wide()

2022-07-08T15:36:26Z

host1x_cdma_push_wide() had the assumptions that the last parameter word was a NOP opcode, and that NOP opcodes could be used in all situations. Neither are true with the new job opcode sequence, so adjust the function to not have these assumptions, and instead place an early RESTART opcode when necessary to jump back to the beginning of the pushbuffer. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Initialize syncval in channel_submit()

2022-07-08T15:35:19Z

During the refactoring of channel_submit(), assignment of syncval was moved but it is also used in channel_submit(). Add this assignment back to channel_submit() as well. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Register context bus unconditionally

2022-07-08T14:31:24Z

Conditional registration is a problem for other subsystems which may unwittingly try to interact with host1x_context_device_bus_type in an uninitialised state on non-Tegra platforms. A look under /sys/bus on a typical system already reveals plenty of entries from enabled but otherwise irrelevant configs, so lets keep things simple and register our context bus unconditionally too. Signed-off-by: Robin Murphy Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+

2022-07-08T14:27:53Z

When MLOCK enforcement is enabled, the 0-word write currently done is rejected by the hardware outside of an MLOCK region. As such, on these chips, which also have the newer, more convenient RESTART_W opcode, use that instead to skip over the timed out job. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding