linux/drivers/gpu/ipu-v3, branch v4.2

GPU: ipu: fix lockup caused by pending chained interrupts

2015-07-10T09:02:46Z

Even with the oops fixed by a previous patch, the system still fails to kexec, due to a stuck chained interrupt locking the system. We must disable the child interrupts prior to setting up the irq chip to ensure we don't get stuck here. Signed-off-by: Russell King Signed-off-by: Philipp Zabel

GPU: ipu: Fix race in installing IPU chained IRQ handler

2015-06-18T12:03:08Z

The IPU code was installing its chained interrupt handler (which enables the interrupt) before it was setting its data, which provokes an oops on kexec. Fix this by converting to irq_set_chained_handler_and_data(). [drm] Initialized drm 1.1.0 20060810 imx-drm display-subsystem: parent device of /soc/aips-bus@02000000/ldb@020e0008/lvds-channel@1 is not available imx-drm display-subsystem: parent device of /soc/aips-bus@02000000/ldb@020e0008/lvds-channel@1 is not available Unable to handle kernel NULL pointer dereference at virtual address 00000070 pgd = c0004000 [00000070] *pgd=00000000 Internal error: Oops: 5 [#1] SMP ARM Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.0-rc6+ #1693 Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) task: d74c0000 ti: d74aa000 task.ti: d74aa000 PC is at ipu_irq_handle+0x28/0xd8 LR is at ipu_irq_handler+0x6c/0xc0 pc : [] lr : [] psr: 200001d3 sp : d74abbd0 ip : d74abc00 fp : d74abbfc r10: 000001e0 r9 : c0085154 r8 : 00000009 r7 : 00000000 r6 : 00000000 r5 : d74abc04 r4 : c0a6b6a8 r3 : 00000000 r2 : 00000009 r1 : d74abc04 r0 : 00000000 Flags: nzCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel Control: 10c5387d Table: 10004059 DAC: 00000015 Process swapper/0 (pid: 1, stack limit = 0xd74aa210) Stack: (0xd74abbd0 to 0xd74ac000) Backtrace: [] (ipu_irq_handle) from [] (ipu_irq_handler+0x6c/0xc0) [] (ipu_irq_handler) from [] (generic_handle_irq+0x28/0x38) [] (generic_handle_irq) from [] (__handle_domain_irq+0x5c/0xb8) [] (__handle_domain_irq) from [] (gic_handle_irq+0x28/0x68) [] (gic_handle_irq) from [] (__irq_svc+0x44/0x5c) [] (_raw_spin_unlock_irqrestore) from [] (__irq_put_desc_unlock+0x1c/0x40) [] (__irq_put_desc_unlock) from [] (__irq_set_handler+0x54/0x5c) [] (__irq_set_handler) from [] (ipu_probe+0x29c/0x708) [] (ipu_probe) from [] (platform_drv_probe+0x50/0xac) [] (platform_drv_probe) from [] (driver_probe_device+0x1d4/0x278) Signed-off-by: Russell King Cc: Alexandre Courbot Cc: Hans Ulli Kroll Cc: Jason Cooper Cc: Lee Jones Cc: Linus Walleij Cc: Thierry Reding Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/E1Z4z02-0002SI-Br@rmk-PC.arm.linux.org.uk Signed-off-by: Thomas Gleixner

Merge tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux into drm-next

2015-04-13T07:28:57Z

imx-drm changes to use media bus formats and LDB drm_panel support - Add media bus formats needed by imx-drm - Switch to use media bus formats to describe the pixel format on the internal parallel bus between display interface and encoders - Some preparations for TV Output via TVEv2 on i.MX5 - Add drm_panel support to the i.MX LVDS driver, allow to determine the bus pixel format from the panel descriptor. * tag 'imx-drm-next-2015-03-31' of git://git.pengutronix.de/git/pza/linux: drm/imx: imx-ldb: allow to determine bus format from the connected panel drm/imx: imx-ldb: reset display clock input when disabling LVDS drm/imx: imx-ldb: add drm_panel support drm/imx: consolidate bus format variable names drm/imx: switch to use media bus formats Add RGB666_1X24_CPADHI media bus format Add YUV8_1X24 media bus format Add BGR888_1X24 and GBR888_1X24 media bus formats Add LVDS RGB media bus formats Add RGB444_1X12 and RGB565_1X16 media bus formats drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 drm/imx: Add support for interlaced scanout

gpu: ipu-v3: turns out the IPU can only downsize 4:1

2015-03-31T10:03:55Z

The value for downsizing 8:1 is marked as reserved in the technical reference manual and the documentation states downsizing capability up to 4:1 only. Signed-off-by: Philipp Zabel

gpu: ipu-v3: limit pixel clock divider to 8-bits

2015-03-31T10:03:54Z

The DI pixel clock divider bit field is only 8 bits wide for the integer part, so limit the divider to the 1...255 interval before deciding whether the internal clock can be used and before writing to the register. Reported-by: Felix Mellmann Signed-off-by: Philipp Zabel

drm/imx: consolidate bus format variable names

2015-03-31T09:59:34Z

This patch consolidates the different interface_pix_fmt, pixel_fmt, pix_fmt, and pixfmt variables to a common name "bus_format" wherever they describe the pixel format on the bus between display controller and encoder hardware. At the same time, it renames imx_drm_panel_format to imx_drm_set_bus_format. Signed-off-by: Philipp Zabel Tested-by: Emil Renner Berthing

drm/imx: switch to use media bus formats

2015-03-31T09:59:34Z

imx-drm internally misused the V4L2_PIX_FMT constants, which are supposed to describe the pixel format of frame buffers in memory, to describe the pixel format on the bus between the display controller and the encoder hardware. Now that MEDIA_BUS_FMT constants are available to drm drivers, use those instead. Signed-off-by: Philipp Zabel Tested-by: Emil Renner Berthing

gpu: ipu-v3: do not divide by zero if the pixel clock is too large

2015-02-23T16:18:59Z

Even if an unsupported mode with a pixel clock larger than two times the 264 MHz IPU HSP clock is set, don't divide by zero. Signed-off-by: Philipp Zabel

Merge tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux into drm-next

2015-02-11T05:35:26Z

imx-drm fixes for IPUv3 DC and i.MX5 IPUv3 IC and TVE - Corrected handling of wait_for_completion_timeout return value when disabling IPUv3 DC channels - Fixed error return value propagation in TVE mode_set - Fixed IPUv3 register offsets for IC module on i.MX51 and i.MX53 * tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: Fix IC control register offset drm: imx: imx-tve: Check and propagate the errors gpu: ipu-v3: wait_for_completion_timeout does not return negative status

gpu: ipu-v3: Fix IC control register offset

2015-01-27T15:28:01Z

The IC register offset is at +0x20000 relative to the control module registers on all IPUv3 versions. This patch fixes wrong values for i.MX51 and i.MX53. Signed-off-by: Philipp Zabel