linux/drivers/gpu/ipu-v3, branch v5.0

gpu: ipu-v3: pre: don't trigger update if buffer address doesn't change

2019-01-23T10:56:44Z

On a NOP double buffer update where current buffer address is the same as the next buffer address, the SDW_UPDATE bit clears too late. As we are now using this bit to determine when it is safe to signal flip completion to userspace this will delay completion of atomic commits where one plane doesn't change the buffer by a whole frame period. Fix this by remembering the last buffer address and just skip the double buffer update if it would not change the buffer address. Signed-off-by: Lucas Stach [p.zabel@pengutronix.de: initialize last_bufaddr in ipu_pre_configure] Signed-off-by: Philipp Zabel

gpu: ipu-v3: Fix CSI offsets for imx53

2019-01-17T13:59:02Z

The CSI offsets are wrong for both CSI0 and CSI1. They are at physical address 0x1e030000 and 0x1e038000 respectively. Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit") Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: Fix i.MX51 CSI control registers offset

2019-01-17T13:58:55Z

The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative to the control module registers on IPUv3EX. This patch fixes wrong values for i.MX51 CSI0/CSI1. Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit") Signed-off-by: Alexander Shiyan Signed-off-by: Philipp Zabel

gpu: ipu-v3: image-convert: allow three rows or columns

2018-11-05T13:40:08Z

If width or height are in the [2049, 3072] range, allow to use just three tiles in this dimension, instead of four. Signed-off-by: Philipp Zabel Acked-by: Steve Longerbeam Tested-by: Steve Longerbeam

gpu: ipu-v3: image-convert: disable double buffering if necessary

2018-11-05T13:40:08Z

Double-buffering only works if tile sizes are the same and the resizing coefficient does not change between tiles, even for non-planar formats. Signed-off-by: Philipp Zabel Acked-by: Steve Longerbeam Tested-by: Steve Longerbeam

gpu: ipu-v3: image-convert: add some ASCII art to the exposition

2018-11-05T13:40:08Z

Visualize the scaling and rotation pipeline with some ASCII art diagrams. Remove the FIXME comment about missing seam prevention. Signed-off-by: Philipp Zabel Acked-by: Steve Longerbeam

gpu: ipu-v3: image-convert: fix bytesperline adjustment

2018-11-05T13:40:08Z

For planar formats, bytesperline does not depend on BPP. It must always be larger than width and aligned to tile width alignment restrictions. The input bytesperline to ipu_image_convert_adjust() may be uninitialized, so don't rely on input bytesperline as the minimum value for clamp_align(). Use 2 << w_align as the minimum instead. Signed-off-by: Philipp Zabel [slongerbeam@gmail.com: clamp input bytesperline] Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: image-convert: relax alignment restrictions

2018-11-05T13:40:08Z

For the planar but U/V-packed formats NV12 and NV16, 8 pixel width alignment is good enough to fulfill the 8 byte stride requirement. If we allow the input 8-pixel DMA bursts to overshoot the end of the line, the only input alignment restrictions are dictated by the pixel format and 8-byte aligned line start address. Since different tile sizes are allowed, the output tile with / height alignment doesn't need to be multiplied by number of columns / rows. Signed-off-by: Philipp Zabel [slongerbeam@gmail.com: Bring in the fixes to format width and height alignment restrictions from imx-media-mem2mem.c.] Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: image-convert: fix debug output for varying tile sizes

2018-11-05T13:40:07Z

Since tile dimensions now vary between tiles, add debug output for each tile's position and dimensions. Signed-off-by: Philipp Zabel Acked-by: Steve Longerbeam Tested-by: Steve Longerbeam

gpu: ipu-v3: image-convert: select optimal seam positions

2018-11-05T13:40:07Z

Select seam positions that minimize distortions during seam hiding while satifying input and output IDMAC, rotator, and image format constraints. This code looks for aligned output seam positions that minimize the difference between the fractional corresponding ideal input positions and the input positions rounded to alignment requirements. Since now tiles can be sized differently, alignment restrictions of the complete image can be relaxed in the next step. Signed-off-by: Philipp Zabel Acked-by: Steve Longerbeam Tested-by: Steve Longerbeam