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<title>linux/drivers/gpu, branch v6.13</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.13</id>
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<updated>2025-01-17T03:49:26Z</updated>
<entry>
<title>Merge tag 'drm-fixes-2025-01-17' of https://gitlab.freedesktop.org/drm/kernel</title>
<updated>2025-01-17T03:49:26Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2025-01-17T03:49:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d'/>
<id>urn:sha1:9bffa1ad25b8b3b95d8f463e5c24dabe3c87d54d</id>
<content type='text'>
Pull drm fixes from Dave Airlie:
 "Final(?) set of fixes for 6.13, I think the holidays finally caught up
  with everyone, the misc changes are 2 weeks worth, otherwise amdgpu
  and xe are most of it. The largest pieces is a new test so I'm not too
  worried about that.

  kunit:
   - Fix W=1 build for kunit tests

  bridge:
   - Handle YCbCr420 better in bridge code, with tests
   - itee-it6263 error handling fix

  amdgpu:
   - SMU 13 fix
   - DP MST fixes
   - DCN 3.5 fix
   - PSR fixes
   - eDP fix
   - VRR fix
   - Enforce isolation fixes
   - GFX 12 fix
   - PSP 14.x fix

  xe:
   - Add steering info support for GuC register lists
   - Add means to wait for reset and synchronous reset
   - Make changing ccs_mode a synchronous action
   - Add missing mux registers
   - Mark ComputeCS read mode as UC on iGPU, unblocking ULLS on iGPU

  i915:
   - Relax clear color alignment to 64 bytes [fb]

  v3d:
   - Fix warn when unloading v3d

  nouveau:
   - Fix cross-device fence handling in nouveau
   - Fix backlight regression for macbooks 5,1

  vmwgfx:
   - Fix BO reservation handling in vmwgfx"

* tag 'drm-fixes-2025-01-17' of https://gitlab.freedesktop.org/drm/kernel: (33 commits)
  drm/xe: Mark ComputeCS read mode as UC on iGPU
  drm/xe/oa: Add missing VISACTL mux registers
  drm/xe: make change ccs_mode a synchronous action
  drm/xe: introduce xe_gt_reset and xe_gt_wait_for_reset
  drm/xe/guc: Adding steering info support for GuC register lists
  drm/bridge: ite-it6263: Prevent error pointer dereference in probe()
  drm/v3d: Ensure job pointer is set to NULL after job completion
  drm/vmwgfx: Add new keep_resv BO param
  drm/vmwgfx: Remove busy_places
  drm/vmwgfx: Unreserve BO on error
  drm/amdgpu: fix fw attestation for MP0_14_0_{2/3}
  drm/amdgpu: always sync the GFX pipe on ctx switch
  drm/amdgpu: disable gfxoff with the compute workload on gfx12
  drm/amdgpu: Fix Circular Locking Dependency in AMDGPU GFX Isolation
  drm/i915/fb: Relax clear color alignment to 64 bytes
  drm/amd/display: Disable replay and psr while VRR is enabled
  drm/amd/display: Fix PSR-SU not support but still call the amdgpu_dm_psr_enable
  nouveau/fence: handle cross device fences properly
  drm/tests: connector: Add ycbcr_420_allowed tests
  drm/connector: hdmi: Validate supported_formats matches ycbcr_420_allowed
  ...
</content>
</entry>
<entry>
<title>Merge tag 'drm-xe-fixes-2025-01-16' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes</title>
<updated>2025-01-17T00:38:45Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-01-16T22:54:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9b1c673a1648cc3501a3b7719db2bec931cf00f7'/>
<id>urn:sha1:9b1c673a1648cc3501a3b7719db2bec931cf00f7</id>
<content type='text'>
Driver Changes:
- Add steering info support for GuC register lists (Jesus Narvaez)
- Add means to wait for reset and synchronous reset (Maciej)
- Make changing ccs_mode a synchronous action (Maciej)
- Add missing mux registers (Ashutosh)
- Mark ComputeCS read mode as UC on iGPU, unblocking ULLS on iGPU (Matt Brost)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Thomas Hellstrom &lt;thomas.hellstrom@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/Z4ll3F1anLEwCvrf@fedora
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-fixes-2025-01-15' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes</title>
<updated>2025-01-16T22:48:12Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-01-16T22:48:11Z</published>
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<id>urn:sha1:cfaf51adaf4e0b1850c84e05c81e879dd571c17c</id>
<content type='text'>
- Relax clear color alignment to 64 bytes [fb] (Ville Syrjälä)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Tvrtko Ursulin &lt;tursulin@igalia.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/Z4fdIVf68qsqIpiN@linux
</content>
</entry>
<entry>
<title>drm/xe: Mark ComputeCS read mode as UC on iGPU</title>
<updated>2025-01-16T19:03:11Z</updated>
<author>
<name>Matthew Brost</name>
<email>matthew.brost@intel.com</email>
</author>
<published>2025-01-14T00:25:07Z</published>
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<id>urn:sha1:b1231ff7ea0689d04040a44864c265bc11612fa8</id>
<content type='text'>
RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
structure. Having this as WB blocks ULLS from being enabled. Change to
UC to unblock ULLS on iGPU.

v2:
 - Drop internal communications commnet, bspec is updated

Cc: Balasubramani Vivekanandan &lt;balasubramani.vivekanandan@intel.com&gt;
Cc: Michal Mrozek &lt;michal.mrozek@intel.com&gt;
Cc: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Cc: José Roberto de Souza &lt;jose.souza@intel.com&gt;
Cc: stable@vger.kernel.org
Fixes: 328e089bfb37 ("drm/xe: Leverage ComputeCS read L3 caching")
Signed-off-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Acked-by: Michal Mrozek &lt;michal.mrozek@intel.com&gt;
Reviewed-by: Stuart Summers &lt;stuart.summers@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250114002507.114087-1-matthew.brost@intel.com
(cherry picked from commit 758debf35b9cda5450e40996991a6e4b222899bd)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'amd-drm-fixes-6.13-2025-01-15' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes</title>
<updated>2025-01-16T07:05:15Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-01-16T02:33:52Z</published>
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<id>urn:sha1:cf8182d33798966146c7eaab7209b606939a17c5</id>
<content type='text'>
amd-drm-fixes-6.13-2025-01-15:

amdgpu:
- SMU 13 fix
- DP MST fixes
- DCN 3.5 fix
- PSR fixes
- eDP fix
- VRR fix
- Enforce isolation fixes
- GFX 12 fix
- PSP 14.x fix

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250115151602.210704-1-alexander.deucher@amd.com
</content>
</entry>
<entry>
<title>Merge tag 'drm-misc-fixes-2025-01-15' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes</title>
<updated>2025-01-16T01:54:14Z</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2025-01-16T01:54:13Z</published>
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<id>urn:sha1:fa6493440f084c5ba8e30dce84158cbfeac86311</id>
<content type='text'>
drm-misc-fixes for v6.13:

- itee-it6263 error handling fix.
- Fix warn when unloading v3d.
- Fix W=1 build for kunit tests.
- Fix backlight regression for macbooks 5,1 in nouveau.
- Handle YCbCr420 better in bridge code, with tests.
- Fix cross-device fence handling in nouveau.
- Fix BO reservation handling in vmwgfx.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Maarten Lankhorst &lt;maarten.lankhorst@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/a89adcd5-2042-4e7f-93f4-2b299bb1ef17@linux.intel.com
</content>
</entry>
<entry>
<title>drm/xe/oa: Add missing VISACTL mux registers</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Ashutosh Dixit</name>
<email>ashutosh.dixit@intel.com</email>
</author>
<published>2025-01-11T02:15:39Z</published>
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<id>urn:sha1:79a21fc921d7aafaf69d00b4938435b81bf66022</id>
<content type='text'>
Add missing VISACTL mux registers required for some OA
config's (e.g. RenderPipeCtrl).

Fixes: cdf02fe1a94a ("drm/xe/oa/uapi: Add/remove OA config perf ops")
Cc: stable@vger.kernel.org
Signed-off-by: Ashutosh Dixit &lt;ashutosh.dixit@intel.com&gt;
Reviewed-by: Umesh Nerlige Ramappa &lt;umesh.nerlige.ramappa@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20250111021539.2920346-1-ashutosh.dixit@intel.com
(cherry picked from commit c26f22dac3449d8a687237cdfc59a6445eb8f75a)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: make change ccs_mode a synchronous action</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Maciej Patelczyk</name>
<email>maciej.patelczyk@intel.com</email>
</author>
<published>2024-12-11T11:17:27Z</published>
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<id>urn:sha1:b26de02cf903b5182588c0df91a6e1b512f7d3f3</id>
<content type='text'>
If ccs_mode is being modified via
   /sys/class/drm/cardX/device/tileY/gtY/ccs_mode
the asynchronous reset is triggered and the write returns immediately.

With that some test receive false information about number of CCS engines
or even fail if they proceed without delay after changing the ccs_mode.

Changing the ccs_mode change from async to sync to prevent failures in
tests.

Signed-off-by: Maciej Patelczyk &lt;maciej.patelczyk@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Fixes: f3bc5bb4d53d ("drm/xe: Allow userspace to configure CCS mode")
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241211111727.1481476-3-maciej.patelczyk@intel.com
Signed-off-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
(cherry picked from commit 480fb9806e2e073532f7786166287114c696b340)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: introduce xe_gt_reset and xe_gt_wait_for_reset</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Maciej Patelczyk</name>
<email>maciej.patelczyk@intel.com</email>
</author>
<published>2024-12-11T11:17:26Z</published>
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<id>urn:sha1:5db89168c408871d306e9fb669e494a1444da8ee</id>
<content type='text'>
Add synchronous version gt reset as there are few places where it
is expected.
Also add a wait helper to wait until gt reset is done.

Signed-off-by: Maciej Patelczyk &lt;maciej.patelczyk@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Fixes: f3bc5bb4d53d ("drm/xe: Allow userspace to configure CCS mode")
Reviewed-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241211111727.1481476-2-maciej.patelczyk@intel.com
Signed-off-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
(cherry picked from commit 155c77f45f63dd58a37eeb0896b0b140ab785836)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe/guc: Adding steering info support for GuC register lists</title>
<updated>2025-01-15T10:32:50Z</updated>
<author>
<name>Jesus Narvaez</name>
<email>jesus.narvaez@intel.com</email>
</author>
<published>2024-12-12T19:01:00Z</published>
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<id>urn:sha1:64192bb2e52d48cfccd8373b0ad565bb9ce3d2e6</id>
<content type='text'>
The guc_mmio_reg interface supports steering, but it is currently not
implemented. This will allow the GuC to control steering of MMIO
registers after save-restore and avoid reading from fused off MCR
register instances.

Fixes: 9c57bc08652a ("drm/xe/lnl: Drop force_probe requirement")
Signed-off-by: Jesus Narvaez &lt;jesus.narvaez@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Cc: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Cc: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Reviewed-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Signed-off-by: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20241212190100.3768068-1-jesus.narvaez@intel.com
(cherry picked from commit ee5a1321df90891d59d83b7c9d5b6c5b755d059d)
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
</content>
</entry>
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