<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/kvm/vmx.h, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2008-01-30T16:01:18Z</updated>
<entry>
<title>KVM: Move arch dependent files to new directory arch/x86/kvm/</title>
<updated>2008-01-30T16:01:18Z</updated>
<author>
<name>Avi Kivity</name>
<email>avi@qumranet.com</email>
</author>
<published>2007-12-16T09:02:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=edf884172e9828c6234b254208af04655855038d'/>
<id>urn:sha1:edf884172e9828c6234b254208af04655855038d</id>
<content type='text'>
This paves the way for multiple architecture support.  Note that while
ioapic.c could potentially be shared with ia64, it is also moved.

Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: wbinvd exiting</title>
<updated>2008-01-30T15:53:01Z</updated>
<author>
<name>Eddie Dong</name>
<email>eddie.dong@intel.com</email>
</author>
<published>2007-11-11T10:28:35Z</published>
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<id>urn:sha1:e5edaa01c4cea5f60c617fac989c6458df0ecc4e</id>
<content type='text'>
Add wbinvd VM Exit support to prepare for pass-through
device cache emulation and also enhance real time
responsiveness.

Signed-off-by: Yaozu (Eddie) Dong &lt;eddie.dong@intel.com&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: Comment VMX primary/secondary exec ctl definitions</title>
<updated>2008-01-30T15:53:01Z</updated>
<author>
<name>Eddie Dong</name>
<email>eddie.dong@intel.com</email>
</author>
<published>2007-11-11T10:27:20Z</published>
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<id>urn:sha1:8a70cc3d0f4877f862ac9cace2e61e4e5116b502</id>
<content type='text'>
Add comments for secondary/primary Processor-Based VM-execution controls.

Signed-off-by: Yaozu (Eddie) Dong &lt;eddie.dong@intel.com&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: Use vmx to inject real-mode interrupts</title>
<updated>2008-01-30T15:53:00Z</updated>
<author>
<name>Avi Kivity</name>
<email>avi@qumranet.com</email>
</author>
<published>2007-11-08T16:19:20Z</published>
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<id>urn:sha1:9c5623e3e42e94927d02a6693875badf15692970</id>
<content type='text'>
Instead of injecting real-mode interrupts by writing the interrupt frame into
guest memory, abuse vmx by injecting a software interrupt.  We need to
pretend the software interrupt instruction had a length &gt; 0, so we have to
adjust rip backward.

This lets us not to mess with writing guest memory, which is complex and also
sleeps.

Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: Enable memory mapped TPR shadow (FlexPriority)</title>
<updated>2008-01-30T15:52:58Z</updated>
<author>
<name>Sheng Yang</name>
<email>sheng.yang@intel.com</email>
</author>
<published>2007-10-29T01:40:42Z</published>
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<id>urn:sha1:f78e0e2ee498e8f847500b565792c7d7634dcf54</id>
<content type='text'>
This patch based on CR8/TPR patch, and enable the TPR shadow (FlexPriority)
for 32bit Windows.  Since TPR is accessed very frequently by 32bit
Windows, especially SMP guest, with FlexPriority enabled, we saw significant
performance gain.

Signed-off-by: Sheng Yang &lt;sheng.yang@intel.com&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: CodingStyle cleanup</title>
<updated>2008-01-30T15:52:50Z</updated>
<author>
<name>Mike Day</name>
<email>ncmike@ncultra.org</email>
</author>
<published>2007-10-08T13:02:08Z</published>
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<id>urn:sha1:d77c26fce93d07802db97498959587eb9347b31d</id>
<content type='text'>
Signed-off-by: Mike D. Day &lt;ncmike@ncultra.org&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: Use shadow TPR/cr8 for 64-bits guests</title>
<updated>2007-10-13T08:18:26Z</updated>
<author>
<name>Yang, Sheng</name>
<email>sheng.yang@intel.com</email>
</author>
<published>2007-09-12T10:03:11Z</published>
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<id>urn:sha1:6e5d865c0b9679b00b5e5f0754c9fc2b6b9894d6</id>
<content type='text'>
This patch enables TPR shadow of VMX on CR8 access. 64bit Windows using
CR8 access TPR frequently. The TPR shadow can improve the performance of
access TPR by not causing vmexit.

Signed-off-by: Sheng Yang &lt;sheng.yang@intel.com&gt;
Signed-off-by: Yaozu (Eddie) Dong &lt;eddie.dong@intel.com&gt;
Signed-off-by: Qing He &lt;qing.he@intel.com&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: Remove a duplicated ia32e mode vm entry control</title>
<updated>2007-10-13T08:18:23Z</updated>
<author>
<name>Li, Xin B</name>
<email>xin.b.li@intel.com</email>
</author>
<published>2007-08-01T18:49:10Z</published>
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<id>urn:sha1:1e4e6e00136b82a5595de903c28912afee1178cb</id>
<content type='text'>
Remove a duplicated ia32e mode VM Entry control definition and use the
proper one.

Signed-off-by: Xin Li &lt;xin.b.li@intel.com&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: VMX: Import some constants of vmcs from IA32 SDM</title>
<updated>2007-10-13T08:18:19Z</updated>
<author>
<name>Yang, Sheng</name>
<email>sheng.yang@intel.com</email>
</author>
<published>2007-07-25T09:17:06Z</published>
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<id>urn:sha1:62b3ffb8b357a791491726cff8d395027e5245b7</id>
<content type='text'>
This patch mainly imports some constants and rename two exist constants
of vmcs according to IA32 SDM.

It also adds two constants to indicate Lock bit and Enable bit in
MSR_IA32_FEATURE_CONTROL, and replace the hardcode _5_ with these two
bits.

Signed-off-by: Sheng Yang &lt;sheng.yang@intel.com&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
<entry>
<title>KVM: Use standard CR4 flags, tighten checking</title>
<updated>2007-10-13T08:18:18Z</updated>
<author>
<name>Rusty Russell</name>
<email>rusty@rustcorp.com.au</email>
</author>
<published>2007-07-17T13:34:16Z</published>
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<id>urn:sha1:66aee91aaab8f998d28a61ed7733be17ad8e6d8f</id>
<content type='text'>
On this machine (Intel), writing to the CR4 bits 0x00000800 and
0x00001000 cause a GPF.  The Intel manual is a little unclear, but
AFIACT they're reserved, too.

Also fix spelling of CR4_RESEVED_BITS.

Signed-off-by: Rusty Russell &lt;rusty@rustcorp.com.au&gt;
Signed-off-by: Avi Kivity &lt;avi@qumranet.com&gt;
</content>
</entry>
</feed>
