linux/drivers/mailbox, branch v5.12

treewide: change my e-mail address, fix my name

2021-04-09T21:54:23Z

Change my e-mail address to kabel@kernel.org, and fix my name in non-code parts (add diacritical mark). Link: https://lkml.kernel.org/r/20210325171123.28093-2-kabel@kernel.org Signed-off-by: Marek Behún Cc: Bartosz Golaszewski Cc: Greg Kroah-Hartman Cc: Jassi Brar Cc: Linus Walleij Cc: Pavel Machek Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

mailbox: arm_mhuv2: Skip calling kfree() with invalid pointer

2021-02-22T19:34:27Z

It is possible that 'data' passed to kfree() is set to a error value instead of allocated space. Make sure it doesn't get called with invalid pointer. Fixes: 5a6338cce9f4 ("mailbox: arm_mhuv2: Add driver") Cc: v5.11 # v5.11 Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Viresh Kumar Signed-off-by: Jassi Brar

mailbox: tegra-hsp: Set lockdep class dynamically

2021-02-15T05:28:40Z

On Tegra194, due to both BPMP and TCU using mailboxes, we get a lockdep spew at boot. Both are using different instances of HSP, so this is harmless. As such give each HSP instance a different lockdep class. Signed-off-by: Mikko Perttunen Signed-off-by: Jassi Brar

mailbox: sprd: correct definition of SPRD_OUTBOX_FIFO_FULL

2021-02-15T05:28:20Z

According to the specification, bit[2] represents SPRD_OUTBOX_FIFO_FULL, not bit[0], so correct it. Fixes: ca27fc26cd22 ("mailbox: sprd: Add Spreadtrum mailbox driver") Signed-off-by: Magnum Shan Signed-off-by: Chunyan Zhang Reviewed-by: Baolin Wang Signed-off-by: Jassi Brar

mailbox: arm_mhuv2: make remove callback return void

2021-02-15T05:27:16Z

My build tests failed to catch that amba driver that would have needed adaption in commit 3fd269e74f2f ("amba: Make the remove callback return void"). Change the remove function to make the driver build again. Reported-by: kernel test robot Fixes: 3fd269e74f2f ("amba: Make the remove callback return void") Signed-off-by: Uwe Kleine-König Acked-by: Viresh Kumar Signed-off-by: Jassi Brar

mailbox: arm_mhuv2: Fix sparse warnings

2021-02-15T05:26:31Z

This patch fixes a bunch of sparse warnings in the newly added arm_mhuv2 driver. drivers/mailbox/arm_mhuv2.c:506:24: warning: incorrect type in argument 1 (different address spaces) drivers/mailbox/arm_mhuv2.c:506:24: expected void const volatile [noderef] __iomem *addr drivers/mailbox/arm_mhuv2.c:506:24: got unsigned int [usertype] * drivers/mailbox/arm_mhuv2.c:547:42: warning: incorrect type in argument 2 (different address spaces) drivers/mailbox/arm_mhuv2.c:547:42: expected unsigned int [usertype] *reg drivers/mailbox/arm_mhuv2.c:547:42: got unsigned int [noderef] __iomem * drivers/mailbox/arm_mhuv2.c:625:42: warning: incorrect type in argument 2 (different address spaces) drivers/mailbox/arm_mhuv2.c:625:42: expected unsigned int [usertype] *reg drivers/mailbox/arm_mhuv2.c:625:42: got unsigned int [noderef] __iomem * drivers/mailbox/arm_mhuv2.c:972:24: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:973:22: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:993:25: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1026:24: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1027:22: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1048:17: warning: dereference of noderef expression Reported-by: kernel test robot Signed-off-by: Viresh Kumar Signed-off-by: Jassi Brar

mailbox: qcom: Add support for SDX55 APCS IPC

2021-02-15T05:25:35Z

In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Jassi Brar

mailbox: omap: Add support for K3 AM64x SoCs

2021-02-15T05:23:41Z

The AM64x SoC contains a Mailbox IP instance with multiple clusters in the MAIN domain, and is a variant of the IP on current AM65x and J721E SoCs. The AM64x SoC has only 8 clusters with no interrupts routed to the A53 core on the first 2 clusters. The interrupt outputs from the IP do not go through any Interrupt Routers and are hard-wired to each processor, with only couple of interrupts from each cluster reaching the A53 core. The IP is also not built with the K3 safety feature in hardware. Add the support for this IP through a new compatible. Signed-off-by: Suman Anna Signed-off-by: Jassi Brar

mailbox: qcom: Add SC8180X apcs compatible

2021-02-15T05:22:21Z

The Qualcomm SC8180X platform has a APSS block exposing the usual IPC bits, add a compatible for this. Signed-off-by: Bjorn Andersson Signed-off-by: Jassi Brar

mailbox: arm_mhuv2: Add driver

2020-12-10T01:26:02Z

This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox controller. This is based on the accepted DT bindings of the controller and supports combination of both transport protocols, i.e. doorbell and data-transfer. Transmitting and receiving data through the mailbox framework is done through struct arm_mhuv2_mbox_msg. Based on the initial work done by Morten Borup Petersen from ARM. Co-developed-by: Tushar Khandelwal Signed-off-by: Tushar Khandelwal Tested-by: Usama Arif Signed-off-by: Viresh Kumar Signed-off-by: Jassi Brar