<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/mailbox, branch v5.15</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.15</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.15'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-09-01T03:57:45Z</updated>
<entry>
<title>mailbox: cmdq: add multi-gce clocks support for mt8195</title>
<updated>2021-09-01T03:57:45Z</updated>
<author>
<name>jason-jh.lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2021-08-31T07:09:03Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=85dfdbfc13ea9614a2168ce4a7d2cd089d84cb64'/>
<id>urn:sha1:85dfdbfc13ea9614a2168ce4a7d2cd089d84cb64</id>
<content type='text'>
For the design of GCE hardware event signal transportation,
evnet rx will send the event signal to all GCE event merges
after receiving the event signal from the other hardware.

Because GCE event merges need to response to event rx, their
clocks must be enabled at that time.

To make sure all the gce clock is enabled while receiving the
hardware event, each cmdq mailbox should enable or disable
the others gce clk at the same time.

Signed-off-by: jason-jh.lin &lt;jason-jh.lin@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: cmdq: add mediatek mailbox support for mt8195</title>
<updated>2021-09-01T03:57:39Z</updated>
<author>
<name>jason-jh.lin</name>
<email>jason-jh.lin@mediatek.com</email>
</author>
<published>2021-08-31T07:09:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8d4f5a9e012abb7919f7b63656ea571f22789918'/>
<id>urn:sha1:8d4f5a9e012abb7919f7b63656ea571f22789918</id>
<content type='text'>
Add mt8195 compatible name in the driver data of cmdq mailbox driver.

Signed-off-by: jason-jh.lin &lt;jason-jh.lin@mediatek.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: qcom-apcs-ipc: Add compatible for MSM8953 SoC</title>
<updated>2021-08-30T05:29:29Z</updated>
<author>
<name>Vladimir Lypak</name>
<email>junak.pub@gmail.com</email>
</author>
<published>2021-08-10T16:44:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e5c11ee3106072ef4b949eca93db160f55e6b55b'/>
<id>urn:sha1:e5c11ee3106072ef4b949eca93db160f55e6b55b</id>
<content type='text'>
MSM8953 has an APCS block similar to MSM8916 but with different clocks
which are spread over 2MB IO region next to it.

Signed-off-by: Vladimir Lypak &lt;junak.pub@gmail.com&gt;
Signed-off-by: Sireesh Kodali &lt;sireeshkodali@protonmail.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: qcom: Add support for SM6115 APCS IPC</title>
<updated>2021-08-30T05:28:34Z</updated>
<author>
<name>Iskren Chernev</name>
<email>iskren.chernev@gmail.com</email>
</author>
<published>2021-06-27T18:58:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dc2b8edfa3b3e691fa43694c4bd1e16b682393e1'/>
<id>urn:sha1:dc2b8edfa3b3e691fa43694c4bd1e16b682393e1</id>
<content type='text'>
Qcom SM4250/6115, have APCS mailbox setup similar to msm8998 and
msm8916.

Signed-off-by: Iskren Chernev &lt;iskren.chernev@gmail.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>soc: mediatek: cmdq: add address shift in jump</title>
<updated>2021-08-30T05:21:38Z</updated>
<author>
<name>Yongqiang Niu</name>
<email>yongqiang.niu@mediatek.com</email>
</author>
<published>2021-08-02T07:52:26Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8b60ed2b1674b78ebc433a11efa7d48821229037'/>
<id>urn:sha1:8b60ed2b1674b78ebc433a11efa7d48821229037</id>
<content type='text'>
Add address shift when compose jump instruction
to compatible with 35bit format.

Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Reviewed-by: Nicolas Boichat &lt;drinkcat@chromium.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: cmdq: add mt8192 support</title>
<updated>2021-08-30T05:20:36Z</updated>
<author>
<name>Yongqiang Niu</name>
<email>yongqiang.niu@mediatek.com</email>
</author>
<published>2021-08-02T07:46:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=84fd4201b78b96f8d31f6a2624be27ad6306a9bc'/>
<id>urn:sha1:84fd4201b78b96f8d31f6a2624be27ad6306a9bc</id>
<content type='text'>
add mt8192 support

Signed-off-by: Yongqiang Niu &lt;yongqiang.niu@mediatek.com&gt;
Signed-off-by: Hsin-Yi Wang &lt;hsinyi@chromium.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a module</title>
<updated>2021-08-30T04:50:15Z</updated>
<author>
<name>Amit Pundir</name>
<email>amit.pundir@linaro.org</email>
</author>
<published>2021-07-16T07:49:46Z</published>
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<id>urn:sha1:8d7e5908c0bcf8a0abc437385e58e49abab11a93</id>
<content type='text'>
This patch enables the qcom_ipcc driver to be loaded as a
module. IPCC is fairly core to system, so as such it should
never be unloaded. It registers as a mailbox + irq controller
and the irq controller drivers in kernel are not supposed to
be unloaded as they don't have the visibility over the clients
consuming the irqs. Hence adding supress_bind_attrs to disable
bind/unbind via sysfs.

Signed-off-by: Amit Pundir &lt;amit.pundir@linaro.org&gt;
Reviewed-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: sti: quieten kernel-doc warnings</title>
<updated>2021-08-30T04:50:12Z</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2021-07-23T18:25:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=23e6a7ca464ed2b9d949520e07f7e0735bc025f4'/>
<id>urn:sha1:23e6a7ca464ed2b9d949520e07f7e0735bc025f4</id>
<content type='text'>
Use kernel-doc struct notation for the mailbox structs to prevent
these kernel-doc warnings:

   drivers/mailbox/mailbox-sti.c:39: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * STi Mailbox device data
   drivers/mailbox/mailbox-sti.c:63: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * STi Mailbox platform specific configuration
   drivers/mailbox/mailbox-sti.c:74: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * STi Mailbox allocated channel information

Also move the field descriptions ahead of the function description as
is expected in kernel-doc. This prevents another kernel-doc warning.

Fixes: 9ef4546cbd7e ("mailbox: Add support for ST's Mailbox IP")
Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Cc: Aditya Srivastava &lt;yashsri421@gmail.com&gt;
Cc: Lee Jones &lt;lee.jones@linaro.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mbox: add polarfire soc system controller mailbox</title>
<updated>2021-06-26T17:06:48Z</updated>
<author>
<name>Conor Dooley</name>
<email>conor.dooley@microchip.com</email>
</author>
<published>2021-06-24T15:00:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=83d7b1560810e038e1d07ca6bff41edaeae29725'/>
<id>urn:sha1:83d7b1560810e038e1d07ca6bff41edaeae29725</id>
<content type='text'>
This driver adds support for the single mailbox channel of the MSS
system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
<entry>
<title>mailbox: imx: Avoid using val uninitialized in imx_mu_isr()</title>
<updated>2021-06-26T17:06:18Z</updated>
<author>
<name>Nathan Chancellor</name>
<email>nathan@kernel.org</email>
</author>
<published>2021-06-21T18:56:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e80a7e7eafcd5e75bf8c73164cae954b3f0addbc'/>
<id>urn:sha1:e80a7e7eafcd5e75bf8c73164cae954b3f0addbc</id>
<content type='text'>
Clang warns:

drivers/mailbox/imx-mailbox.c:284:2: warning: variable 'val' is used
uninitialized whenever switch default is taken
[-Wsometimes-uninitialized]
        default:
        ^~~~~~~
drivers/mailbox/imx-mailbox.c:288:7: note: uninitialized use occurs here
        if (!val)
             ^~~
drivers/mailbox/imx-mailbox.c:263:9: note: initialize the variable 'val'
to silence this warning
        u32 val, ctrl;
               ^
                = 0
1 warning generated.

Prior to commit 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register
array"), val was always initialized in imx_mu_isr() but now, it is not
initialized in the default case. Return IRQ_NONE like the statement
below does and add a message that there is an unhandled type for this
switch statement so that it can be updated.

Fixes: 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array")
Link: https://github.com/ClangBuiltLinux/linux/issues/1404
Signed-off-by: Nathan Chancellor &lt;nathan@kernel.org&gt;
Signed-off-by: Jassi Brar &lt;jaswinder.singh@linaro.org&gt;
</content>
</entry>
</feed>
