linux/drivers/memory/Kconfig, branch v5.1

memory: pl353: Add driver for arm pl353 static memory controller

2018-12-13T15:07:04Z

Add driver for arm pl353 static memory controller. This controller is used in Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices. Signed-off-by: Naga Sureshkumar Relli Reviewed-by: Linus Walleij Signed-off-by: Michal Simek

drivers/memory/Kconfig: Add CONFIG_OF dependency

2018-07-31T07:46:06Z

JZ4780_NEMC doesn't depend on OF, and if OF isn't enabled we get this error: drivers/memory/jz4780-nemc.c: In function ‘jz4780_nemc_num_banks’: drivers/memory/jz4780-nemc.c:72:10: error: implicit declaration of function ‘of_read_number’; did you mean ‘down_read_nested’? [-Werror=implicit-function-declaration] bank = of_read_number(prop, 1); ^~~~~~~~~~~~~~ down_read_nested Make JZ4780_NEMC depend on OF. Fixes: ab99e11062c1 ("memory: jz4780-nemc: Allow selection of this driver when COMPILE_TEST=y") Reported-by: Randy Dunlap Signed-off-by: Anders Roxell Acked-by: Randy Dunlap Signed-off-by: Miquel Raynal

memory: jz4780-nemc: Allow selection of this driver when COMPILE_TEST=y

2018-07-19T21:14:11Z

It just makes maintainers' life easier by allowing them to compile-test this driver without having MACH_JZ4780 enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by: Boris Brezillon Acked-by: Paul Burton Signed-off-by: Miquel Raynal

memory: fsl_ifc: Allow selection of this driver when COMPILE_TEST=y

2018-07-18T08:10:21Z

It just makes maintainers' life easier by allowing them to compile-test this driver without having FSL_SOC, ARCH_LAYERSCAPE or SOC_LS1021A enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by: Boris Brezillon Signed-off-by: Miquel Raynal

memory: tegra: Squash tegra20-mc into common tegra-mc driver

2018-04-30T08:10:00Z

Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver in a preparation for the upcoming MC hot reset controls implementation, avoiding code duplication. Note that this currently doesn't report the value of MC_GART_ERROR_REQ because it is located within the GART register area and cannot be safely accessed from the MC driver (this happens to work only by accident). The proper solution is to integrate the GART driver with the MC driver, much like is done for the Tegra SMMU, but that is an invasive change and will be part of a separate patch series. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: ti-emif-sram: introduce relocatable suspend/resume handlers

2017-12-03T03:27:17Z

Certain SoCs like Texas Instruments AM335x and AM437x require parts of the EMIF PM code to run late in the suspend sequence from SRAM, such as saving and restoring the EMIF context and placing the memory into self-refresh. One requirement for these SoCs to suspend and enter its lowest power mode, called DeepSleep0, is that the PER power domain must be shut off. Because the EMIF (DDR Controller) resides within this power domain, it will lose context during a suspend operation, so we must save it so we can restore once we resume. However, we cannot execute this code from external memory, as it is not available at this point, so the code must be executed late in the suspend path from SRAM. This patch introduces a ti-emif-sram driver that includes several functions written in ARM ASM that are relocatable so the PM SRAM code can use them. It also allocates a region of writable SRAM to be used by the code running in the executable region of SRAM to save and restore the EMIF context. It can export a table containing the absolute addresses of the available PM functions so that other SRAM code can branch to them. This code is required for suspend/resume on AM335x and AM437x to work. In addition to this, to be able to share data structures between C and the ti-emif-sram-pm assembly code, we can automatically generate all of the C struct member offsets and sizes as macros by processing emif-asm-offsets.c into assembly code and then extracting the relevant data as is done for the generated platform asm-offsets.h files. Acked-by: Tony Lindgren Acked-by: Russell King Signed-off-by: Dave Gerlach Signed-off-by: Santosh Shilimkar

Merge tag 'for-linus-20170510' of git://git.infradead.org/linux-mtd

2017-05-11T17:44:22Z

Pull MTD updates from Brian Norris: "NAND, from Boris: - some minor fixes/improvements on existing drivers (fsmc, gpio, ifc, davinci, brcmnand, omap) - a huge cleanup/rework of the denali driver accompanied with core fixes/improvements to simplify the driver code - a complete rewrite of the atmel driver to support new DT bindings make future evolution easier - the addition of per-vendor detection/initialization steps to avoid extending the nand_ids table with more extended-id entries SPI NOR, from Cyrille: - fixes in the hisi, intel and Mediatek SPI controller drivers - fixes to some SPI flash memories not supporting the Chip Erase command. - add support to some new memory parts (Winbond, Macronix, Micron, ESMT). - add new driver for the STM32 QSPI controller And a few fixes for Gemini and Versatile platforms on physmap-of" * tag 'for-linus-20170510' of git://git.infradead.org/linux-mtd: (100 commits) MAINTAINERS: Update NAND subsystem git repositories mtd: nand: gpio: update binding mtd: nand: add ooblayout for old hamming layout mtd: oxnas_nand: Allocating more than necessary in probe() dt-bindings: mtd: Document the STM32 QSPI bindings mtd: mtk-nor: set controller's address width according to nor flash mtd: spi-nor: add driver for STM32 quad spi flash controller mtd: nand: brcmnand: Check flash #WP pin status before nand erase/program mtd: nand: davinci: add comment on NAND subpage write status on keystone mtd: nand: omap2: Fix partition creation via cmdline mtdparts mtd: nand: NULL terminate a of_device_id table mtd: nand: Fix a couple error codes mtd: nand: allow drivers to request minimum alignment for passed buffer mtd: nand: allocate aligned buffers if NAND_OWN_BUFFERS is unset mtd: nand: denali: allow to override revision number mtd: nand: denali_dt: use pdev instead of ofdev for platform_device mtd: nand: denali_dt: remove dma-mask DT property mtd: nand: denali: support 64bit capable DMA engine mtd: nand: denali_dt: enable HW_ECC_FIXUP for Altera SOCFPGA variant mtd: nand: denali: support HW_ECC_FIXUP capability ...

memory: atmel-ebi: Simplify SMC config code

2017-04-27T08:25:06Z

New helpers/macros have been to atmel-smc.h introduced to simplify SMC regs manipulation. Rework the code to use those helpers, and simplify the ->xlate_config(), ->get_config() and ->apply_config() implementations. SMC configs are now stored in a struct atmel_smc_cs_conf object that directly contains registers values, which should help implementing ->suspend()/->resume() hooks. We can also get rid of those regmap fields (and the associated ->init() hook) which are not longer needed thanks to the atmel_[h]smc_cs_conf_{apply,get}() helpers. Signed-off-by: Boris Brezillon Acked-by: Nicolas Ferre Signed-off-by: Lee Jones

memory: ifc: Update dependency of IFC for LS1021A

2017-03-16T09:30:02Z

As Freescale/NXP IFC controller is available on LS1021A, the dependency for LS1021A is added. LS1021A is an earlier product and is not compatible with later LayerScape architecture. So ARCH_LAYERSCAPE can't cover LS1021A. Signed-off-by: Alison Wang Signed-off-by: Boris Brezillon

memory: davinci: add support for da8xx DDR2/mDDR controller

2016-11-14T11:48:34Z

Create a new driver for the da8xx DDR2/mDDR controller and implement support for writing to the Peripheral Bus Burst Priority Register. Reviewed-by: Kevin Hilman Acked-by: Rob Herring Signed-off-by: Bartosz Golaszewski [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori