<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/memory/tegra, branch v5.5</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.5</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.5'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-11-18T12:54:40Z</updated>
<entry>
<title>memory: tegra30-emc: Fix panic on suspend</title>
<updated>2019-11-18T12:54:40Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-11-15T16:26:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=030d2829f4c22e675e21904f32ab60f659174e72'/>
<id>urn:sha1:030d2829f4c22e675e21904f32ab60f659174e72</id>
<content type='text'>
Trying to suspend driver results in a crash if timings aren't available in
device-tree.

Reported-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Fixes: e34212c75a68 ("memory: tegra: Introduce Tegra30 EMC driver")
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Consolidate registers definition into common header</title>
<updated>2019-11-11T13:55:27Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=141bef44e123c101c0da0443ab6b3cfa750f251a'/>
<id>urn:sha1:141bef44e123c101c0da0443ab6b3cfa750f251a</id>
<content type='text'>
The Memory Controller registers definition is sparse and duplicated,
let's consolidate everything into a common place for consistency.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Ensure timing control debug features are disabled</title>
<updated>2019-11-11T13:55:27Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=77b7182ff18dd5a83d938ab42772db5cb82c75b8'/>
<id>urn:sha1:77b7182ff18dd5a83d938ab42772db5cb82c75b8</id>
<content type='text'>
Timing control debug features should be disabled at a boot time, but you
never now and hence it's better to disable them explicitly because some of
those features are crucial for the driver to do a proper thing.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Introduce Tegra30 EMC driver</title>
<updated>2019-11-11T13:55:27Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e34212c75a68990f7215d64d725c61e57ca70357'/>
<id>urn:sha1:e34212c75a68990f7215d64d725c61e57ca70357</id>
<content type='text'>
Introduce driver for the External Memory Controller (EMC) found on Tegra30
chips, it controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Do not handle error from wait_for_completion_timeout()</title>
<updated>2019-11-11T13:55:26Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:36Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=88c5bfecaa36c1b92666f9f0a02b4fa36e7f6337'/>
<id>urn:sha1:88c5bfecaa36c1b92666f9f0a02b4fa36e7f6337</id>
<content type='text'>
Contrary to its wait_for_completion_timeout_interruptible() sibling, the
wait_for_completion_timeout() function does not return an error.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Increase handshake timeout on Tegra20</title>
<updated>2019-11-11T13:55:26Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:35Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b56563d0138c3622634e50f3dbca1359b5e7237b'/>
<id>urn:sha1:b56563d0138c3622634e50f3dbca1359b5e7237b</id>
<content type='text'>
Turned out that it could take over a millisecond under some circumstances,
like running on a very low CPU/memory frequency. TRM says that handshake
happens when there is a "safe" moment, but not explains exactly what that
moment is. Apparently at least memory should be idling and thus the low
frequency should be a reasonable cause for a longer handshake delay.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Print a brief info message about EMC timings</title>
<updated>2019-11-11T13:55:26Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:34Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f541efaa7459621fb68eb6e54546e195ab48d43a'/>
<id>urn:sha1:f541efaa7459621fb68eb6e54546e195ab48d43a</id>
<content type='text'>
During boot print how many memory timings got the driver and what's the
RAM code. This is a very useful information when something is wrong with
boards memory timing.

Suggested-by: Marc Dietrich &lt;marvin24@gmx.de&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Pre-configure debug register on Tegra20</title>
<updated>2019-11-11T13:55:25Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c72396f941fb9d4113fb2fe18c00ae75c6c92c3e'/>
<id>urn:sha1:c72396f941fb9d4113fb2fe18c00ae75c6c92c3e</id>
<content type='text'>
The driver expects certain debug features to be disabled in order to
work properly. Let's disable them explicitly for consistency and to not
rely on a boot state.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Include io.h instead of iopoll.h</title>
<updated>2019-11-11T13:55:25Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d039cf2834e9eb7cfd14f245172ca4f4a67c106b'/>
<id>urn:sha1:d039cf2834e9eb7cfd14f245172ca4f4a67c106b</id>
<content type='text'>
The register polling code was gone, but the included header change was
missed. Fix it up for consistency.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Adapt for Tegra20 clock driver changes</title>
<updated>2019-11-11T13:55:25Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-08-11T21:00:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=77ab499dca5d7426a84f76988b3f84e7c9db7e12'/>
<id>urn:sha1:77ab499dca5d7426a84f76988b3f84e7c9db7e12</id>
<content type='text'>
Now Tegra20 and Tegra30 EMC drivers should provide clock-rounding
functionality using the new Tegra clock driver API.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
