linux/drivers/memory/tegra, branch v5.8

memory: tegra: Correct debugfs clk rate-range on Tegra124

2020-03-11T14:24:16Z

Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 6b9acd935546 ("memory: tegra: Refashion EMC debugfs interface on Tegra124") Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Correct debugfs clk rate-range on Tegra30

2020-03-11T14:24:16Z

Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8cee32b40040 ("memory: tegra: Implement EMC debugfs interface on Tegra30") Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Correct debugfs clk rate-range on Tegra20

2020-03-11T14:24:15Z

Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8209eefa3d37 ("memory: tegra: Implement EMC debugfs interface on Tegra20") Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra30-emc: Correct error message for timed out auto calibration

2020-01-10T14:48:48Z

The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra30-emc: Firm up hardware programming sequence

2020-01-10T14:48:40Z

Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra30-emc: Firm up suspend/resume sequence

2020-01-10T14:47:18Z

The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Correct reset value of xusb_hostr

2020-01-10T14:34:06Z

According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen Signed-off-by: Thierry Reding

memory: tegra: Add support for the Tegra194 memory controller

2020-01-09T18:38:38Z

The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding

memory: tegra: Only include support for enabled SoCs

2020-01-09T18:35:54Z

The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding

memory: tegra: Support DVFS on Tegra186 and later

2020-01-09T18:35:54Z

Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding