<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/memory/tegra, branch v6.7</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v6.7</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v6.7'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2023-11-09T21:37:28Z</updated>
<entry>
<title>Merge tag 'iommu-updates-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu</title>
<updated>2023-11-09T21:37:28Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2023-11-09T21:37:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4bbdb725a36b0d235f3b832bd0c1e885f0442d9f'/>
<id>urn:sha1:4bbdb725a36b0d235f3b832bd0c1e885f0442d9f</id>
<content type='text'>
Pull iommu updates from Joerg Roedel:
 "Core changes:
   - Make default-domains mandatory for all IOMMU drivers
   - Remove group refcounting
   - Add generic_single_device_group() helper and consolidate drivers
   - Cleanup map/unmap ops
   - Scaling improvements for the IOVA rcache depot
   - Convert dart &amp; iommufd to the new domain_alloc_paging()

  ARM-SMMU:
   - Device-tree binding update:
       - Add qcom,sm7150-smmu-v2 for Adreno on SM7150 SoC
   - SMMUv2:
       - Support for Qualcomm SDM670 (MDSS) and SM7150 SoCs
   - SMMUv3:
       - Large refactoring of the context descriptor code to move the CD
         table into the master, paving the way for '-&gt;set_dev_pasid()'
         support on non-SVA domains
   - Minor cleanups to the SVA code

  Intel VT-d:
   - Enable debugfs to dump domain attached to a pasid
   - Remove an unnecessary inline function

  AMD IOMMU:
   - Initial patches for SVA support (not complete yet)

  S390 IOMMU:
   - DMA-API conversion and optimized IOTLB flushing

  And some smaller fixes and improvements"

* tag 'iommu-updates-v6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (102 commits)
  iommu/dart: Remove the force_bypass variable
  iommu/dart: Call apple_dart_finalize_domain() as part of alloc_paging()
  iommu/dart: Convert to domain_alloc_paging()
  iommu/dart: Move the blocked domain support to a global static
  iommu/dart: Use static global identity domains
  iommufd: Convert to alloc_domain_paging()
  iommu/vt-d: Use ops-&gt;blocked_domain
  iommu/vt-d: Update the definition of the blocking domain
  iommu: Move IOMMU_DOMAIN_BLOCKED global statics to ops-&gt;blocked_domain
  Revert "iommu/vt-d: Remove unused function"
  iommu/amd: Remove DMA_FQ type from domain allocation path
  iommu: change iommu_map_sgtable to return signed values
  iommu/virtio: Add __counted_by for struct viommu_request and use struct_size()
  iommu/vt-d: debugfs: Support dumping a specified page table
  iommu/vt-d: debugfs: Create/remove debugfs file per {device, pasid}
  iommu/vt-d: debugfs: Dump entry pointing to huge page
  iommu/vt-d: Remove unused function
  iommu/arm-smmu-v3-sva: Remove bond refcount
  iommu/arm-smmu-v3-sva: Remove unused iommu_sva handle
  iommu/arm-smmu-v3: Rename cdcfg to cd_table
  ...
</content>
</entry>
<entry>
<title>Merge tag 'memory-controller-drv-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers</title>
<updated>2023-10-16T21:00:46Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2023-10-16T21:00:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e855cbf28b6d46ac87dab630b1e56fd4a8fe9845'/>
<id>urn:sha1:e855cbf28b6d46ac87dab630b1e56fd4a8fe9845</id>
<content type='text'>
Memory controller drivers for v6.7

1. Atmel: Use __counted_by annotation.
2. Tegra: Add Tegra234 clients for RCE and VI.
3. Cleanup:
 - Use device_get_match_data() to simplify the code,
 - Make "additionalProperties: true" explicit in Devicetree bindings.

* tag 'memory-controller-drv-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: Use device_get_match_data()
  memory: tegra: Add Tegra234 clients for RCE and VI
  dt-bindings: memory-controllers: Make "additionalProperties: true" explicit
  memory: atmel-ebi: Annotate struct atmel_ebi_dev with __counted_by

Link: https://lore.kernel.org/r/20231016074013.28286-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Set BPMP msg flags to reset IPC channels</title>
<updated>2023-10-13T12:23:41Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2023-10-09T10:05:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f344675a34383ae26a8230f4b1cd99cbd0defebd'/>
<id>urn:sha1:f344675a34383ae26a8230f4b1cd99cbd0defebd</id>
<content type='text'>
Set the 'TEGRA_BPMP_MESSAGE_RESET' bit in newly added 'flags' field
of 'struct tegra_bpmp_message' to request for the reset of BPMP IPC
channels. This is used along with the 'suspended' check in BPMP driver
for handling early bandwidth requests due to the hotplug of CPU's
during system resume before the driver gets resumed.

Fixes: f41e1442ac5b ("cpufreq: tegra194: add OPP support and set bandwidth")
Co-developed-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add Tegra234 clients for RCE and VI</title>
<updated>2023-10-12T13:30:25Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2023-10-12T10:49:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9def28f3b8634e4f1fa92a77ccb65fbd2d03af34'/>
<id>urn:sha1:9def28f3b8634e4f1fa92a77ccb65fbd2d03af34</id>
<content type='text'>
Add the Tegra234 memory client entries for the Real-time Camera Engine
(RCE) and Video Input (VI) devices.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20231012104909.48518-1-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>iommu/tegra-gart: Remove tegra-gart</title>
<updated>2023-09-25T09:40:54Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@nvidia.com</email>
</author>
<published>2023-09-13T13:43:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c462944901319cb52ec0d0382dcea64f4f6f70e8'/>
<id>urn:sha1:c462944901319cb52ec0d0382dcea64f4f6f70e8</id>
<content type='text'>
Thierry says this is not used anymore, and doesn't think it makes sense as
an iommu driver. The HW it supports is about 10 years old now and newer HW
uses different IOMMU drivers.

As this is the only driver with a GART approach, and it doesn't really
meet the driver expectations from the IOMMU core, let's just remove it
so we don't have to think about how to make it fit in.

It has a number of identified problems:
 - The assignment of iommu_groups doesn't match the HW behavior

 - It claims to have an UNMANAGED domain but it is really an IDENTITY
   domain with a translation aperture. This is inconsistent with the core
   expectation for security sensitive operations

 - It doesn't implement a SW page table under struct iommu_domain so
   * It can't accept a map until the domain is attached
   * It forgets about all maps after the domain is detached
   * It doesn't clear the HW of maps once the domain is detached
     (made worse by having the wrong groups)

Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Cc: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Lu Baolu &lt;baolu.lu@linux.intel.com&gt;
Reviewed-by: Jerry Snitselaar &lt;jsnitsel@redhat.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
Link: https://lore.kernel.org/r/6-v8-81230027b2fa+9d-iommu_all_defdom_jgg@nvidia.com
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: add MC client for Tegra234 GPU</title>
<updated>2023-08-05T07:01:31Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2023-08-01T12:10:23Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=35bd78cf252245f11dd1c9d5f1b414c25e727b5a'/>
<id>urn:sha1:35bd78cf252245f11dd1c9d5f1b414c25e727b5a</id>
<content type='text'>
Add the Non-ISO MC client for the Tegra234 GPU to the
tegra234_mc_clients table.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Link: https://lore.kernel.org/r/20230801121023.27841-1-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: Explicitly include correct DT includes</title>
<updated>2023-07-25T20:09:37Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2023-07-14T17:47:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0b4838717fff5e24d97742e79ba1ee46cbfbf4b6'/>
<id>urn:sha1:0b4838717fff5e24d97742e79ba1ee46cbfbf4b6</id>
<content type='text'>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20230714174717.4059518-1-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Prefer octal over symbolic permissions</title>
<updated>2023-07-25T20:09:36Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2023-07-14T15:01:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6e1547f9873b0cea840625081ee4e5d7dd26661a'/>
<id>urn:sha1:6e1547f9873b0cea840625081ee4e5d7dd26661a</id>
<content type='text'>
checkpatch recommends using octal permissions instead of symbolic
permissions. Switch the debugfs files to use the former to silence
these warnings.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20230714150116.2823766-1-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported</title>
<updated>2023-07-25T20:09:36Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2023-06-21T13:43:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=0a7e4578567a3270ba35ebde4e0ce2795fa55384'/>
<id>urn:sha1:0a7e4578567a3270ba35ebde4e0ce2795fa55384</id>
<content type='text'>
Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the
BPMP-FW before making the MRQ request. Currently, if the BPMP-FW
doesn't support this MRQ, then the "tegra186_emc_probe" fails.
Due to this the Memory Interconnect initialization also doesn't
happen. Memory Interconnect is not dependent on this MRQ and can
initialize even when this MRQ is not supported in any platform.
The check ensures that the MRQ is called only when it is supported
by the BPMP-FW and Interconnect initializes independent of this MRQ.
Also, moved the code to new function for better readability.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20230621134400.23070-4-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add clients used by DRM in Tegra234</title>
<updated>2023-07-25T20:09:36Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2023-06-21T13:43:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b18e525990acb67f214f6b2528fae292ac9cf641'/>
<id>urn:sha1:b18e525990acb67f214f6b2528fae292ac9cf641</id>
<content type='text'>
Add entries for VIC, NVDEC, NVENC, NVJPG memory controller
clients into the 'tegra_234_mc_clients' table.

Signed-off-by: Johnny Liu &lt;johnliu@nvidia.com&gt;
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20230621134400.23070-3-sumitg@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
</feed>
