<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/memory, branch v5.1</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.1</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.1'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-01-16T12:54:13Z</updated>
<entry>
<title>memory: tegra: Clean up error messages</title>
<updated>2019-01-16T12:54:13Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f2dcded1be0d024870b5a4ef8e4a587857f303b4'/>
<id>urn:sha1:f2dcded1be0d024870b5a4ef8e4a587857f303b4</id>
<content type='text'>
Make all messages to start with a lower case and don't unnecessarily go
over 80 chars in the code.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Do not ask for IRQ sharing</title>
<updated>2019-01-16T12:54:13Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=33ea002aadd9cbf1836a13c71e424f113bce635a'/>
<id>urn:sha1:33ea002aadd9cbf1836a13c71e424f113bce635a</id>
<content type='text'>
Memory Controller driver never shared IRQ with any other driver and very
unlikely that it will. Hence there is no need to request IRQ sharing and
the corresponding flag can be dropped safely.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Do not try to probe SMMU on Tegra20</title>
<updated>2019-01-16T12:54:13Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=568ece5bab24d41bec4d1610439277032840a133'/>
<id>urn:sha1:568ece5bab24d41bec4d1610439277032840a133</id>
<content type='text'>
Tegra20 doesn't have SMMU. Move out checking of the SMMU presence from
the SMMU driver into the Memory Controller driver. This change makes code
consistent in regards to how GART/SMMU presence checking is performed.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>iommu/tegra: gart: Integrate with Memory Controller driver</title>
<updated>2019-01-16T12:54:12Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ce2785a75dbca27375f3723f4e697a2a8dc096ee'/>
<id>urn:sha1:ce2785a75dbca27375f3723f4e697a2a8dc096ee</id>
<content type='text'>
The device-tree binding has been changed. There is no separate GART device
anymore, it is squashed into the Memory Controller. Integrate GART module
with the MC in a way it is done for the SMMU on Tegra30+.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Use relaxed versions of readl/writel</title>
<updated>2019-01-16T12:54:12Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:55Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=45594c683ef780f20f11b1e0018b933b6ff5d9a1'/>
<id>urn:sha1:45594c683ef780f20f11b1e0018b933b6ff5d9a1</id>
<content type='text'>
There is no need for inserting of memory barriers to access registers of
Memory Controller. Hence use the relaxed versions of the accessors.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Use of_device_get_match_data()</title>
<updated>2019-01-16T12:54:12Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:54Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=59cd046f7f94543540d82216dbbfd8146db43b70'/>
<id>urn:sha1:59cd046f7f94543540d82216dbbfd8146db43b70</id>
<content type='text'>
There is no need to match device with the DT node since it was already
matched, use of_device_get_match_data() helper to get the match-data.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Read client ID on GART page fault</title>
<updated>2019-01-16T12:54:11Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:53Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b3bb6b858f2a60fe3ac0c3833084386f7dd420e4'/>
<id>urn:sha1:b3bb6b858f2a60fe3ac0c3833084386f7dd420e4</id>
<content type='text'>
With the device tree binding changes, now Memory Controller has access to
GART registers. Hence it is now possible to read client ID on GART page
fault to get information about what memory client causes the fault.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Adapt to Tegra20 device-tree binding changes</title>
<updated>2019-01-16T12:54:11Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:52Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=96efa118c03648fdc76acad9ca8fe018a6be7145'/>
<id>urn:sha1:96efa118c03648fdc76acad9ca8fe018a6be7145</id>
<content type='text'>
The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed as well. Adapt driver to
the DT changes.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Don't invoke Tegra30+ specific memory timing setup on Tegra20</title>
<updated>2019-01-16T12:54:11Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-12-12T20:38:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=be4dbdec2bab8635c7a41573668624ee13d83022'/>
<id>urn:sha1:be4dbdec2bab8635c7a41573668624ee13d83022</id>
<content type='text'>
This fixes irrelevant "tegra-mc 7000f000.memory-controller: no memory
timings for RAM code 0 registered" warning message during of kernels
boot-up on Tegra20.

Fixes: a8d502fd3348 ("memory: tegra: Squash tegra20-mc into common tegra-mc driver")
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Joerg Roedel &lt;jroedel@suse.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2019-01-05T19:30:37Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-01-05T19:30:37Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=b23b0ea3708c3dec599966fc856836aca48835b9'/>
<id>urn:sha1:b23b0ea3708c3dec599966fc856836aca48835b9</id>
<content type='text'>
Pull more ARM SoC updates from Olof Johansson:
 "A few updates that we merged late but are low risk for regressions for
  other platforms (and a few other straggling patches):

   - I mis-tagged the 'drivers' branch, and missed 3 patches. Merged in
     here. They're for a driver for the PL353 SRAM controller and a
     build fix for the qualcomm scm driver.

   - A new platform, RDA Micro RDA8810PL (Cortex-A5 w/ integrated
     Vivante GPU, 256MB RAM, Wifi). This includes some acked
     platform-specific drivers (serial, etc). This also include DTs for
     two boards with this SoC, OrangePi 2G and OrangePi i86.

   - i.MX8 is another new platform (NXP, 4x Cortex-A53 + Cortex-M4, 4K
     video playback offload). This is the first i.MX 64-bit SoC.

   - Some minor updates to Samsung boards (adding a few peripherals in
     DTs).

   - Small rework for SMP bootup on STi platforms.

   - A couple of TEE driver fixes.

   - A couple of new config options (bcm2835 thermal, Uniphier MDMAC)
     enabled in defconfigs"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
  ARM: multi_v7_defconfig: enable CONFIG_UNIPHIER_MDMAC
  arm64: defconfig: Re-enable bcm2835-thermal driver
  MAINTAINERS: Add entry for RDA Micro SoC architecture
  tty: serial: Add RDA8810PL UART driver
  ARM: dts: rda8810pl: Add interrupt support for UART
  dt-bindings: serial: Document RDA Micro UART
  ARM: dts: rda8810pl: Add timer support
  ARM: dts: Add devicetree for OrangePi i96 board
  ARM: dts: Add devicetree for OrangePi 2G IoT board
  ARM: dts: Add devicetree for RDA8810PL SoC
  ARM: Prepare RDA8810PL SoC
  dt-bindings: arm: Document RDA8810PL and reference boards
  dt-bindings: Add RDA Micro vendor prefix
  ARM: sti: remove pen_release and boot_lock
  arm64: dts: exynos: Add Bluetooth chip to TM2(e) boards
  arm64: dts: imx8mq-evk: enable watchdog
  arm64: dts: imx8mq: add watchdog devices
  MAINTAINERS: add i.MX8 DT path to i.MX architecture
  arm64: add support for i.MX8M EVK board
  arm64: add basic DTS for i.MX8MQ
  ...
</content>
</entry>
</feed>
