linux/drivers/memory, branch v5.5

Merge tag 'tegra-for-5.5-memory-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes

2019-12-06T16:28:51Z

memory: tegra: Fixes for v5.5-rc1 This contains a fix for a kernel panic that can occur on suspend if EMC timings are not available in device tree. * tag 'tegra-for-5.5-memory-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Fix panic on suspend Link: https://lore.kernel.org/r/20191204130753.3614278-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2019-12-05T19:43:31Z

Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...

memory: tegra30-emc: Fix panic on suspend

2019-11-18T12:54:40Z

Trying to suspend driver results in a crash if timings aren't available in device-tree. Reported-by: Jon Hunter Fixes: e34212c75a68 ("memory: tegra: Introduce Tegra30 EMC driver") Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Thierry Reding

Merge tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

2019-11-11T21:13:23Z

memory: tegra: Changes for v5.5-rc1 This contains a couple of fixes and adds support for EMC frequency scaling on Tegra30. * tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits clk: tegra: Add Tegra20/30 EMC clock implementation Link: https://lore.kernel.org/r/20191111143836.4027200-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson

memory: tegra: Consolidate registers definition into common header

2019-11-11T13:55:27Z

The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Ensure timing control debug features are disabled

2019-11-11T13:55:27Z

Timing control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Introduce Tegra30 EMC driver

2019-11-11T13:55:27Z

Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Signed-off-by: Thierry Reding

memory: tegra: Do not handle error from wait_for_completion_timeout()

2019-11-11T13:55:26Z

Contrary to its wait_for_completion_timeout_interruptible() sibling, the wait_for_completion_timeout() function does not return an error. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Increase handshake timeout on Tegra20

2019-11-11T13:55:26Z

Turned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Print a brief info message about EMC timings

2019-11-11T13:55:26Z

During boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing. Suggested-by: Marc Dietrich Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding