Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ https://git.shady.money/linux/atom?h=v5.6 2020-01-16T18:45:44Z 2020-01-16T18:45:44Z Olof Johansson olof@lixom.net 2020-01-16T18:45:42Z urn:sha1:c7ce73eb018566222542adfb21f18961d0009286 mvebu drivers for 5.6 (part 1) - Various cleanup on the following drivers: - Turris Mox rWTM firmware - Moxtet bus - Armada 37xx rWTM mailbox - Marvell EBU Device Bus * tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu: mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource memory: mvebu-devbus: convert to devm_platform_ioremap_resource bus: moxtet: declare moxtet_bus_type as static firmware: turris-mox-rwtm: small white space cleanup Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop Signed-off-by: Olof Johansson <olof@lixom.net> 2020-01-16T18:41:48Z Olof Johansson olof@lixom.net 2020-01-16T18:41:47Z urn:sha1:083b4db857310ad269fc49e0019dd0f8fee305d3 memory: tegra: Changes for v5.6-rc1 This adds a couple of fixes for the Tegra30 EMC frequency scaling code and adds support for EMC frequency scaling on Tegra186 and later. * tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence memory: tegra: Correct reset value of xusb_hostr memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later memory: tegra: Add system sleep support memory: tegra: Extract memory client SID programming memory: tegra: Add per-SoC data for Tegra186 memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186 memory: tegra: Implement EMC debugfs interface on Tegra30 memory: tegra: Implement EMC debugfs interface on Tegra20 memory: tegra: Refashion EMC debugfs interface on Tegra124 Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net> 2020-01-10T14:48:48Z Dmitry Osipenko digetx@gmail.com 2019-12-20T02:08:49Z urn:sha1:5e5eca6644873da93f5a32904f43220380f34e88 The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-10T14:48:40Z Dmitry Osipenko digetx@gmail.com 2019-12-20T02:08:48Z urn:sha1:0f8bb9da5aee80d8d1b716e0fc5441575ff0ef21 Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-10T14:47:18Z Dmitry Osipenko digetx@gmail.com 2019-12-20T02:08:47Z urn:sha1:51bb73f93410a30550641f69d14cfb7b43fd2da1 The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-10T14:34:06Z Nicolin Chen nicoleotsuka@gmail.com 2019-12-20T00:29:11Z urn:sha1:5f5636ef1de9174db8333787086a0e105938a2c5 According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-09T18:38:38Z Thierry Reding treding@nvidia.com 2019-12-22T14:10:32Z urn:sha1:a127e690b051df030f5ad2e28b14e8c3a624c145 The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-09T18:35:54Z Thierry Reding treding@nvidia.com 2019-12-22T14:10:31Z urn:sha1:4e04b88633ae9cb38d6bc1d7fd37d2782eab726d The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-09T18:35:54Z Thierry Reding treding@nvidia.com 2019-12-22T14:10:30Z urn:sha1:52d15dd23f0b0f1d1cf87b1581cc5f1f8c22eb0c Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding <treding@nvidia.com> 2020-01-09T18:12:55Z Thierry Reding treding@nvidia.com 2019-12-22T14:10:29Z urn:sha1:177602b006414b02152d3ef670746beb2bfde9cd Add system suspend/resume support for the memory controller found on Tegra186 and later. This is required so that the SID registers can be reprogrammed after their content was lost during system sleep. Signed-off-by: Thierry Reding <treding@nvidia.com>