<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/mmc, branch v4.3</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.3</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.3'/>
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<updated>2015-10-21T08:18:11Z</updated>
<entry>
<title>mmc: core: Fix init_card in 52Mhz</title>
<updated>2015-10-21T08:18:11Z</updated>
<author>
<name>Chaotian Jing</name>
<email>chaotian.jing@mediatek.com</email>
</author>
<published>2015-10-12T09:22:23Z</published>
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<id>urn:sha1:08b137d90eec51b0e90c42e123ca8ceb118d233f</id>
<content type='text'>
Suppose that we got a data crc error, and it triggers the mmc_reset.
mmc_reset will call mmc_send_status to see if HW reset was supported.
before issue CMD13, it will do retune, and if EMMC was in HS400 mode,
it will reduce frequency to 52Mhz firstly, then results in card init
was doing at 52Mhz.
The mmc_send_status was originally only done for mmc_test, should drop
it. And, rename the "eMMC hardware reset" to "Reset test", as we would
also be able to use the test for SD-cards.

Signed-off-by: Chaotian Jing &lt;chaotian.jing@mediatek.com&gt;
Suggested-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Fixes: bd11e8bd03ca ("mmc: core: Flag re-tuning is needed on CRC errors")
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci-of-at91: use SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST quirk</title>
<updated>2015-10-08T17:55:05Z</updated>
<author>
<name>ludovic.desroches@atmel.com</name>
<email>ludovic.desroches@atmel.com</email>
</author>
<published>2015-09-17T08:16:20Z</published>
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<id>urn:sha1:88c6eb0e3b81a30514d21679735fa25d028c2299</id>
<content type='text'>
The Atmel sdhci device needs the
SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST quirk. Without it, the
internal clock could never stabilised when changing the sd clock
frequency.

Signed-off-by: Ludovic Desroches &lt;ludovic.desroches@atmel.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci: add quirk SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST</title>
<updated>2015-10-08T17:55:05Z</updated>
<author>
<name>ludovic.desroches@atmel.com</name>
<email>ludovic.desroches@atmel.com</email>
</author>
<published>2015-09-17T08:16:19Z</published>
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<id>urn:sha1:af951761d01c89eea8f1dcccf8010218e4b55817</id>
<content type='text'>
The Atmel sdhci device needs a new quirk. sdhci_set_clock set the Clock
Control Register to 0 before computing the new value and writing it.
It disables the internal clock which causes a reset mecanism. If we
write the new value before this reset mecanism is done, it will prevent
the stabilisation of the internal clock, so a delay is needed. This
delay is about 2-3 cycles of the base clock. To be safe, a 1 ms delay is
used.

Signed-off-by: Ludovic Desroches &lt;ludovic.desroches@atmel.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci-pxav3: fix error handling of armada_38x_quirks</title>
<updated>2015-10-08T17:24:23Z</updated>
<author>
<name>Marcin Wojtas</name>
<email>mw@semihalf.com</email>
</author>
<published>2015-10-06T01:22:37Z</published>
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<id>urn:sha1:2162d9f41e7c4778b96b8e3b97adcedbadc861f1</id>
<content type='text'>
In case of armada_38x_quirks error, all clocks should be cleaned-up, same
as after mv_conf_mbus_windows failure.

Signed-off-by: Marcin Wojtas &lt;mw@semihalf.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v4.2
Reviewed-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci-pxav3: disable clock inversion for HS MMC cards</title>
<updated>2015-10-08T17:24:23Z</updated>
<author>
<name>Nadav Haklai</name>
<email>nadavh@marvell.com</email>
</author>
<published>2015-10-06T01:22:36Z</published>
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<id>urn:sha1:fa7964147da57b2d40c2db2b6ed98fb7dc934bff</id>
<content type='text'>
According to 'FE-2946959' erratum the clock inversion option is
needed to support slow frequencies when the card input hold time
requirement is high. This setting is not required for high speed
MMC and might cause timing violation.

Signed-off-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v4.2
Reviewed-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: sdhci-pxav3: remove broken clock base quirk for Armada 38x sdhci driver</title>
<updated>2015-10-08T17:24:23Z</updated>
<author>
<name>Nadav Haklai</name>
<email>nadavh@marvell.com</email>
</author>
<published>2015-10-06T01:22:35Z</published>
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<id>urn:sha1:5de76bfcb1e5ac66c57b99e8e193dacac7416f0e</id>
<content type='text'>
shci-pxav3 driver is enabling by default the
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN quirk. However this quirk is not
required for Armada 38x and leads to wrong clock setting in the divider.

Signed-off-by: Nadav Haklai &lt;nadavh@marvell.com&gt;
Signed-off-by: Marcin Wojtas &lt;mw@semihalf.com&gt;
Cc: &lt;stable@vger.kernel.org&gt; # v4.2
Reviewed-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: host: omap_hsmmc: Fix MMC for omap3 legacy booting</title>
<updated>2015-10-08T07:36:13Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2015-10-07T13:22:25Z</published>
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<id>urn:sha1:123e20b14530b57bd75e295961d2c1f8c48455bf</id>
<content type='text'>
Starting with commit 7d607f917008 ("mmc: host: omap_hsmmc: use
devm_regulator_get_optional() for vmmc") MMC on omap3 stopped working
for legacy booting.

This is because legacy booting sets up some of the resource in the
platform init code, and for optional regulators always seem to
return -EPROBE_DEFER for the legacy booting.

Let's fix the issue by checking for device tree based booting for
now. Then when omap3 boots in device tree only mode, this patch
can be just reverted.

Fixes: 7d607f917008 ("mmc: host: omap_hsmmc: use
devm_regulator_get_optional() for vmmc")
Cc: Felipe Balbi &lt;balbi@ti.com&gt;
Cc: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Tested-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>Revert "mmc: host: omap_hsmmc: use regulator_is_enabled to find pbias status"</title>
<updated>2015-10-08T07:35:31Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2015-10-07T13:22:24Z</published>
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<id>urn:sha1:bb2726b52f2abdf46339a2d1293f76b5d5752705</id>
<content type='text'>
This reverts commit c55d7a0553643a7e8f120688b82b594471084d3c.

Without reverting this commit we get "unbalanced disables for pbias_mmc_omap4"
errors on omap4430. It seems that 4430 and 4460 behave in a different way for
the PBIAS regulator registers and until that has been debugged further we
cannot rely on the regulator status registers in hardare on 4430.

Fixes: 7d607f917008 ("mmc: host: omap_hsmmc: use
devm_regulator_get_optional() for vmmc")
Cc: Felipe Balbi &lt;balbi@ti.com&gt;
Cc: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Cc: Nishanth Menon &lt;nm@ti.com&gt;
Cc: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Tested-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: core: fix dead loop of mmc_retune</title>
<updated>2015-09-30T12:54:22Z</updated>
<author>
<name>Chaotian Jing</name>
<email>chaotian.jing@mediatek.com</email>
</author>
<published>2015-09-30T09:37:18Z</published>
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<id>urn:sha1:031277d4d33d33f0174fbb569ca8f68238175617</id>
<content type='text'>
When get a CRC error, start the mmc_retune, it will issue CMD19/CMD21
to do tune, assume there were 10 clock phase need to try, phase 0 to
phase 6 is ok, phase 7 to phase 9 is NG, we try it from 0 to 9, so
the last CMD19/CMD21 will get CRC error, host-&gt;need_retune was set and
cause mmc_retune was called, then dead loop of mmc_retune

Signed-off-by: Chaotian Jing &lt;chaotian.jing@mediatek.com&gt;
Acked-by: Adrian Hunter &lt;adrian.hunter@intel.com&gt;
Fixes: bd11e8bd03ca ("mmc: core: Flag re-tuning is needed on CRC errors")
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
<entry>
<title>mmc: pxamci: fix card detect with slot-gpio API</title>
<updated>2015-09-29T10:17:05Z</updated>
<author>
<name>Robert Jarzmik</name>
<email>robert.jarzmik@free.fr</email>
</author>
<published>2015-09-26T19:41:01Z</published>
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<id>urn:sha1:fd546ee6a7dc4b71ebc6d1205bf72ea3c1c7030a</id>
<content type='text'>
Move pxamci to mmc slot-gpio API to fix interrupt request.

It fixes the case where the card detection is on a gpio expander, on I2C
for example on zylonite board. In this case, the card detect netsted
interrupt is called from a threaded interrupt. The request_irq() fails,
because a hard irq cannot be a nested interrupt from a threaded
interrupt (set __setup_irq()).

This was tested on zylonite and mioa701 boards.

Signed-off-by: Robert Jarzmik &lt;robert.jarzmik@free.fr&gt;
Cc: Petr Cvek &lt;petr.cvek@tul.cz&gt;
Signed-off-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
</content>
</entry>
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