<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/net/phy/realtek, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2026-04-13T23:38:25Z</updated>
<entry>
<title>net: phy: realtek: use LEDCR page number define on RTL8211F</title>
<updated>2026-04-13T23:38:25Z</updated>
<author>
<name>Aleksander Jan Bajkowski</name>
<email>olek2@wp.pl</email>
</author>
<published>2026-04-11T10:51:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=43a2deae3661d0d51f9d39244ceb0a1701ec0006'/>
<id>urn:sha1:43a2deae3661d0d51f9d39244ceb0a1701ec0006</id>
<content type='text'>
Replace the magic number with an existing define for the LEDCR
register page number on the RTL8211F.

Signed-off-by: Aleksander Jan Bajkowski &lt;olek2@wp.pl&gt;
Reviewed-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Link: https://patch.msgid.link/20260411105150.184577-1-olek2@wp.pl
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: convert RTL8211F to .disable_autonomous_eee</title>
<updated>2026-04-12T18:33:23Z</updated>
<author>
<name>Nicolai Buchwitz</name>
<email>nb@tipi-net.de</email>
</author>
<published>2026-04-06T07:13:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=bb14e3b63c63a48307843c82180bc8abb34e1acc'/>
<id>urn:sha1:bb14e3b63c63a48307843c82180bc8abb34e1acc</id>
<content type='text'>
The RTL8211F previously unconditionally disabled PHY-mode EEE in
config_init. Convert this to use the new .disable_autonomous_eee
callback so it is only disabled when the MAC indicates EEE support
via phy_support_eee().

This preserves PHY-autonomous EEE for MACs that do not support EEE,
while still disabling it when the MAC manages LPI.

Signed-off-by: Nicolai Buchwitz &lt;nb@tipi-net.de&gt;
Link: https://patch.msgid.link/20260406-devel-autonomous-eee-v1-3-b335e7143711@tipi-net.de
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: Add property to enable SSC</title>
<updated>2026-04-10T03:01:52Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@mailbox.org</email>
</author>
<published>2026-04-05T23:29:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=84c5a3f00084ffd741a4c3261a58dd10cd5aceaf'/>
<id>urn:sha1:84c5a3f00084ffd741a4c3261a58dd10cd5aceaf</id>
<content type='text'>
Add support for spread spectrum clocking (SSC) on RTL8211F(D)(I)-CG,
RTL8211FS(I)(-VS)-CG, RTL8211FG(I)(-VS)-CG PHYs. The implementation
follows EMI improvement application note Rev. 1.2 for these PHYs.

The current implementation enables SSC for both RXC and SYSCLK clock
signals. Introduce DT properties 'realtek,clkout-ssc-enable',
'realtek,rxc-ssc-enable' and 'realtek,sysclk-ssc-enable' which control
CLKOUT, RXC and SYSCLK SSC spread spectrum clocking enablement on these
signals.

Signed-off-by: Marek Vasut &lt;marek.vasut@mailbox.org&gt;
Link: https://patch.msgid.link/20260405233008.148974-3-marek.vasut@mailbox.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: get rid of magic numbers in rtl8201_config_intr()</title>
<updated>2026-04-09T02:17:17Z</updated>
<author>
<name>Aleksander Jan Bajkowski</name>
<email>olek2@wp.pl</email>
</author>
<published>2026-04-06T20:12:12Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=dbc2bb4e8742068d3d3dc8ebb46d874e5fd953b8'/>
<id>urn:sha1:dbc2bb4e8742068d3d3dc8ebb46d874e5fd953b8</id>
<content type='text'>
Replace the magic numbers with defines. Register names were obtained from
publicly available documentation[1]. This should make it clear what's going
on in the code.

1. RTL8201F/RTL8201FL/RTL8201FN Rev. 1.4 Datasheet
Signed-off-by: Aleksander Jan Bajkowski &lt;olek2@wp.pl&gt;
Reviewed-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Reviewed-by: Nicolai Buchwitz nb@tipi-net.de
Link: https://patch.msgid.link/20260406201222.1043396-1-olek2@wp.pl
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: add RTL8224 polarity support</title>
<updated>2026-03-21T02:12:46Z</updated>
<author>
<name>Damien Dejean</name>
<email>dam.dejean@gmail.com</email>
</author>
<published>2026-03-18T21:55:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=beed9c0e9b53c98bc66d28d46fbe38c347e9aa74'/>
<id>urn:sha1:beed9c0e9b53c98bc66d28d46fbe38c347e9aa74</id>
<content type='text'>
The RTL8224 has a register to configure the polarity of every pair of
each port. It provides device designers more flexbility when wiring the
chip.

Unfortunately, the register is left in an unknown state after a reset.
Thus on devices where the bootloader don't initialize it, the driver has
to do it to detect and use a link.

The MDI polarity swap can be set in the device tree using the property
enet-phy-pair-polarity. The u32 value is a bitfield where bit[0..3]
control the polarity of pairs A..D.

Signed-off-by: Damien Dejean &lt;dam.dejean@gmail.com&gt;
Link: https://patch.msgid.link/20260318215502.106528-5-dam.dejean@gmail.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: add RTL8224 pair order support</title>
<updated>2026-03-21T02:12:46Z</updated>
<author>
<name>Damien Dejean</name>
<email>dam.dejean@gmail.com</email>
</author>
<published>2026-03-18T21:54:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=330296ea9e158758aa65631f5ec64aa74806b7e2'/>
<id>urn:sha1:330296ea9e158758aa65631f5ec64aa74806b7e2</id>
<content type='text'>
The RTL8224 has a register to configure a pair swap (from ABCD order to
DCBA) providing PCB designers more flexbility when wiring the chip. The
swap parameter has to be set correctly for each of the 4 ports before
the chip can detect a link.

After a reset, this register is (unfortunately) left in a random state,
thus it has to be initialized. On most of the devices the bootloader
does it once for all and we can rely on the value set, on some other it
is not and the kernel has to do it.

The MDI pair swap can be set in the device tree using the property
enet-phy-pair-order. The property is set to 0 to keep the default order
(ABCD), or 1 to reverse the pairs (DCBA).

Signed-off-by: Damien Dejean &lt;dam.dejean@gmail.com&gt;
Link: https://patch.msgid.link/20260318215502.106528-3-dam.dejean@gmail.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: Add support for PHY LEDs on RTL8211F-VD</title>
<updated>2026-03-06T02:29:42Z</updated>
<author>
<name>Kryštof Černý</name>
<email>cleverline1mc@gmail.com</email>
</author>
<published>2026-03-04T12:03:10Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=752941e3faf6be26c6b5a118e37bdbaea2b97171'/>
<id>urn:sha1:752941e3faf6be26c6b5a118e37bdbaea2b97171</id>
<content type='text'>
Realtek RTL8211F-VD has the same LED configuration
and registers as RTL8211F.
Use the existing LED related functions for this chip,
so it is possible to also use the netdev trigger.

Tested on ROCK Pi E.

Signed-off-by: Kryštof Černý &lt;cleverline1mc@gmail.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Link: https://patch.msgid.link/20260304-rtl8211fvd-add-leds-v2-1-d50bd8a50f08@gmail.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: simplify bogus paged operations</title>
<updated>2026-01-18T00:12:16Z</updated>
<author>
<name>Daniel Golle</name>
<email>daniel@makrotopia.org</email>
</author>
<published>2026-01-13T03:44:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=650e55f224a575cdb18c984b95036109519502d1'/>
<id>urn:sha1:650e55f224a575cdb18c984b95036109519502d1</id>
<content type='text'>
Only registers 0x10~0x17 are affected by the value in the page
selection register 0x1f. Hence there is no point in using paged
operations when accessing any other registers.
Simplify the driver by using the normal phy_read and phy_write
operations for registers which are anyway not affected by paging.

Signed-off-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Link: https://patch.msgid.link/0c5cbb66ce3e72a011d76f8c3d61ebcac44483bb.1768275364.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: demystify PHYSR register location</title>
<updated>2026-01-18T00:12:16Z</updated>
<author>
<name>Daniel Golle</name>
<email>daniel@makrotopia.org</email>
</author>
<published>2026-01-13T03:44:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=46ff862d376cfadf0f9e36a6edce41a003175708'/>
<id>urn:sha1:46ff862d376cfadf0f9e36a6edce41a003175708</id>
<content type='text'>
Turns out that register address RTL_VND2_PHYSR (0xa434) maps to
Clause-22 register MII_RESV2. Use that to get rid of yet another magic
number, and rename access macros accordingly.

Signed-off-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Link: https://patch.msgid.link/6ed246e0aa3ca8038d2fa432d51518959fb89b6b.1768275364.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: phy: realtek: reunify C22 and C45 drivers</title>
<updated>2026-01-18T00:12:16Z</updated>
<author>
<name>Daniel Golle</name>
<email>daniel@makrotopia.org</email>
</author>
<published>2026-01-13T03:44:25Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=85f75da86a0adc4798d3675aab3365e721a1dbf5'/>
<id>urn:sha1:85f75da86a0adc4798d3675aab3365e721a1dbf5</id>
<content type='text'>
Reunify the split C22/C45 drivers for the RTL8221B-VB-CG 2.5Gbps and
RTL8221B-VM-CG 2.5Gbps PHYs back into a single driver.

This is possible now by using all the driver operations previously used
by the C45 driver, as transparent access to all MMDs including
MDIO_MMD_VEND2 is now possible also over Clause-22 MDIO.

The unified driver will still only use Clause-45 access on any Clause-45
capable busses while still working fine on Clause-22 busses.

Signed-off-by: Daniel Golle &lt;daniel@makrotopia.org&gt;
Link: https://patch.msgid.link/bffcb85fdc20e07056976962d3caaa1be5d0ddb0.1768275364.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
</feed>
