<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/nvmem, branch v5.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-02-07T20:54:13Z</updated>
<entry>
<title>Merge branch 'i2c/for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux</title>
<updated>2020-02-07T20:54:13Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-02-07T20:54:13Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=11777ee8b04acab07c96959e9c6ac6a1603d0958'/>
<id>urn:sha1:11777ee8b04acab07c96959e9c6ac6a1603d0958</id>
<content type='text'>
Pull i2c updates from Wolfram Sang:
 "i2c core:

   - huge improvements and refactorizations of the Linux I2C
     documentation (lots of thanks to Luca for doing it and Jean for the
     careful review)

   - subsystem wide API conversion to i2c_new_client_device()

   - remove obsolete parport-light driver

   - smaller core updates (removal of 'extern', enabling more compile
     testing, use more helper macros)

   - and quite a bunch of driver updates (new IDs, simplifications,
     better PM, support of atomic transfers and other improvements)

  i2c-mux:

   - The main feature is the idle-state rework of the pca954x driver
     from Biwen Li

  at24 driver:

   - minor maintenance: update the license tag, sort headers

   - move support for the write-protect pin into nvmem core

   - add a reference to the new wp-gpios property in nvmem to at25
     bindings

   - add support for regulator and pm_runtime control"

* 'i2c/for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (91 commits)
  i2c: cros-ec-tunnel: Fix ACPI identifier
  i2c: cros-ec-tunnel: Fix slave device enumeration
  i2c: stm32f7: add PM_SLEEP suspend/resume support
  i2c: cadence: Fix wording in i2c-cadence driver
  i2c: cadence: Fix power management order of operations
  i2c: cadence: Fix error printing in case of defer
  i2c: cadence: Handle transfer_size rollover
  i2c: i801: Add support for Intel Comet Lake PCH-V
  docs: i2c: writing-clients: properly name the stop condition
  docs: i2c: i2c-protocol: use same wording as smbus-protocol
  docs: i2c: rename sections so the overall picture is clearer
  docs: i2c: old-module-parameters: use monospace instead of ""
  docs: i2c: old-module-parameters: clarify this is for obsolete kernels
  docs: i2c: old-module-parameters: fix internal hyperlink
  docs: i2c: instantiating-devices: use monospace for sysfs attributes
  docs: i2c: instantiating-devices: rearrange static instatiation
  docs: i2c: instantiating-devices: fix internal hyperlink
  docs: i2c: smbus-protocol: improve I2C Block transactions description
  docs: i2c: smbus-protocol: fix punctuation
  docs: i2c: smbus-protocol: fix typo
  ...
</content>
</entry>
<entry>
<title>nvmem: add QTI SDAM driver</title>
<updated>2020-01-16T19:56:49Z</updated>
<author>
<name>Anirudh Ghayal</name>
<email>aghayal@codeaurora.org</email>
</author>
<published>2020-01-16T16:11:00Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=40ce9798794f972961b5a1c54773ae3daf42cf29'/>
<id>urn:sha1:40ce9798794f972961b5a1c54773ae3daf42cf29</id>
<content type='text'>
QTI SDAM driver allows PMIC peripherals to access the shared memory
that is available on QTI PMICs.

Use subsys_initcall as PMIC SDAM NV memory is accessed by multiple PMIC
drivers (charger, fuel gauge) to store/restore data across reboots
required during their initialization.

Signed-off-by: Anirudh Ghayal &lt;aghayal@codeaurora.org&gt;
Signed-off-by: Shyam Kumar Thella &lt;sthella@codeaurora.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Link: https://lore.kernel.org/r/20200116161100.30637-4-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>nvmem: core: fix memory abort in cleanup path</title>
<updated>2020-01-10T12:52:13Z</updated>
<author>
<name>Bitan Biswas</name>
<email>bbiswas@nvidia.com</email>
</author>
<published>2020-01-09T10:40:17Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=16bb7abc4a6b9defffa294e4dc28383e62a1dbcf'/>
<id>urn:sha1:16bb7abc4a6b9defffa294e4dc28383e62a1dbcf</id>
<content type='text'>
nvmem_cell_info_to_nvmem_cell implementation has static
allocation of name. nvmem_add_cells_from_of() call may
return error and kfree name results in memory abort. Use
kstrdup_const() and kfree_const calls for name alloc and free.

Unable to handle kernel paging request at virtual address ffffffffffe44888
Mem abort info:
  ESR = 0x96000006
  EC = 0x25: DABT (current EL), IL = 32 bits
  SET = 0, FnV = 0
  EA = 0, S1PTW = 0
Data abort info:
  ISV = 0, ISS = 0x00000006
  CM = 0, WnR = 0
swapper pgtable: 64k pages, 48-bit VAs, pgdp=00000000815d0000
[ffffffffffe44888] pgd=0000000081d30803, pud=0000000081d30803,
pmd=0000000000000000
Internal error: Oops: 96000006 [#1] PREEMPT SMP
Modules linked in:
CPU: 2 PID: 43 Comm: kworker/2:1 Tainted
Hardware name: quill (DT)
Workqueue: events deferred_probe_work_func
pstate: a0000005 (NzCv daif -PAN -UAO)
pc : kfree+0x38/0x278
lr : nvmem_cell_drop+0x68/0x80
sp : ffff80001284f9d0
x29: ffff80001284f9d0 x28: ffff0001f677e830
x27: ffff800011b0b000 x26: ffff0001c36e1008
x25: ffff8000112ad000 x24: ffff8000112c9000
x23: ffffffffffffffea x22: ffff800010adc7f0
x21: ffffffffffe44880 x20: ffff800011b0b068
x19: ffff80001122d380 x18: ffffffffffffffff
x17: 00000000d5cb4756 x16: 0000000070b193b8
x15: ffff8000119538c8 x14: 0720072007200720
x13: 07200720076e0772 x12: 07750762072d0765
x11: 0773077507660765 x10: 072f073007300730
x9 : 0730073207380733 x8 : 0000000000000151
x7 : 07660765072f0720 x6 : ffff0001c00e0f00
x5 : 0000000000000000 x4 : ffff0001c0b43800
x3 : ffff800011b0b068 x2 : 0000000000000000
x1 : 0000000000000000 x0 : ffffffdfffe00000
Call trace:
 kfree+0x38/0x278
 nvmem_cell_drop+0x68/0x80
 nvmem_device_remove_all_cells+0x2c/0x50
 nvmem_register.part.9+0x520/0x628
 devm_nvmem_register+0x48/0xa0
 tegra_fuse_probe+0x140/0x1f0
 platform_drv_probe+0x50/0xa0
 really_probe+0x108/0x348
 driver_probe_device+0x58/0x100
 __device_attach_driver+0x90/0xb0
 bus_for_each_drv+0x64/0xc8
 __device_attach+0xd8/0x138
 device_initial_probe+0x10/0x18
 bus_probe_device+0x90/0x98
 deferred_probe_work_func+0x74/0xb0
 process_one_work+0x1e0/0x358
 worker_thread+0x208/0x488
 kthread+0x118/0x120
 ret_from_fork+0x10/0x18
Code: d350feb5 f2dffbe0 aa1e03f6 8b151815 (f94006a0)
---[ end trace 49b1303c6b83198e ]---

Fixes: badcdff107cbf ("nvmem: Convert to using %pOFn instead of device_node.name")
Signed-off-by: Bitan Biswas &lt;bbiswas@nvidia.com&gt;
Cc: stable &lt;stable@vger.kernel.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Link: https://lore.kernel.org/r/20200109104017.6249-5-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>nvmem: imx: ocotp: introduce ocotp_ctrl_reg</title>
<updated>2020-01-10T12:52:12Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-01-09T10:40:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=226c512699ee047b7fae0df297ea0be9e2b629c5'/>
<id>urn:sha1:226c512699ee047b7fae0df297ea0be9e2b629c5</id>
<content type='text'>
Introduce ocotp_ctrl_reg to include the low 16bits mask of CTRL
register.

i.MX chips will have different layout of the low 16bits of CTRL
register, so use ocotp_ctrl_reg will make it clean to add new
chip support.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Link: https://lore.kernel.org/r/20200109104017.6249-4-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>nvmem: imx: scu: correct the fuse word index</title>
<updated>2020-01-10T12:52:12Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-01-09T10:40:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8c4d35aff54042aa80efaabdb7b754b3d74a71d5'/>
<id>urn:sha1:8c4d35aff54042aa80efaabdb7b754b3d74a71d5</id>
<content type='text'>
i.MX8 fuse word row index represented as one 4-bytes word.
Exp:
- MAC0 address layout in fuse:
offset 708: MAC[3] MAC[2] MAC[1] MAC[0]
offset 709: XX     xx     MAC[5] MAC[4]

The original code takes row index * 4 as the offset, this
not exactly match i.MX8 fuse map documentation.

So update code the reflect the truth.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Fugang Duan &lt;fugang.duan@nxp.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Link: https://lore.kernel.org/r/20200109104017.6249-3-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>nvmem: imx: scu: fix write SIP</title>
<updated>2020-01-10T12:52:12Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2020-01-09T10:40:14Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=40bb95dbb8acca35f8d52a833393ddbb01cfa2db'/>
<id>urn:sha1:40bb95dbb8acca35f8d52a833393ddbb01cfa2db</id>
<content type='text'>
SIP number 0xC200000A is for reading, 0xC200000B is for writing.
And the following two args for write are word index, data to write.

Fixes: 885ce72a09d0 ("nvmem: imx: scu: support write")
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Cc: stable &lt;stable@vger.kernel.org&gt;
Link: https://lore.kernel.org/r/20200109104017.6249-2-srinivas.kandagatla@linaro.org
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>nvmem: fix a 'makes pointer from integer without a cast' build warning</title>
<updated>2020-01-10T11:11:30Z</updated>
<author>
<name>Bartosz Golaszewski</name>
<email>bgolaszewski@baylibre.com</email>
</author>
<published>2020-01-10T08:19:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a99d2c6ccd15570a74a39992efa82fd169026b4c'/>
<id>urn:sha1:a99d2c6ccd15570a74a39992efa82fd169026b4c</id>
<content type='text'>
nvmem_register() returns a pointer, not a long int. Use ERR_CAST() to
cast the struct gpio_desc pointer to struct nvmem_device.

Reported-by: kbuild test robot &lt;lkp@intel.com&gt;
Fixes: 2a127da461a9 ("nvmem: add support for the write-protect pin")
Signed-off-by: Bartosz Golaszewski &lt;bgolaszewski@baylibre.com&gt;
Acked-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
</content>
</entry>
<entry>
<title>nvmem: add support for the write-protect pin</title>
<updated>2020-01-09T09:48:54Z</updated>
<author>
<name>Khouloud Touil</name>
<email>ktouil@baylibre.com</email>
</author>
<published>2020-01-07T09:29:19Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2a127da461a9d8d97782d6e82b227041393eb4d2'/>
<id>urn:sha1:2a127da461a9d8d97782d6e82b227041393eb4d2</id>
<content type='text'>
The write-protect pin handling looks like a standard property that
could benefit other users if available in the core nvmem framework.

Instead of modifying all the memory drivers to check this pin, make
the NVMEM subsystem check if the write-protect GPIO being passed
through the nvmem_config or defined in the device tree and pull it
low whenever writing to the memory.

There was a suggestion for introducing the gpiodesc from pdata, but
as pdata is already removed it could be replaced by adding it to
nvmem_config.

Reference: https://lists.96boards.org/pipermail/dev/2018-August/001056.html

Signed-off-by: Khouloud Touil &lt;ktouil@baylibre.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Bartosz Golaszewski &lt;bgolaszewski@baylibre.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2019-12-05T19:43:31Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-12-05T19:43:31Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ec939e4c94bd3ef2fd4f34c15f8aaf79bd0c5ee1'/>
<id>urn:sha1:ec939e4c94bd3ef2fd4f34c15f8aaf79bd0c5ee1</id>
<content type='text'>
Pull ARM SoC driver updates from Olof Johansson:
 "Various driver updates for platforms:

   - A larger set of work on Tegra 2/3 around memory controller and
     regulator features, some fuse cleanups, etc..

   - MMP platform drivers, in particular for USB PHY, and other smaller
     additions.

   - Samsung Exynos 5422 driver for DMC (dynamic memory configuration),
     and ASV (adaptive voltage), allowing the platform to run at more
     optimal operating points.

   - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas

   - Clock/reset control driver for TI/OMAP

   - Meson-A1 reset controller support

   - Qualcomm sdm845 and sda845 SoC IDs for socinfo"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits)
  firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT
  soc: fsl: add RCPM driver
  dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition
  memory: tegra: Consolidate registers definition into common header
  memory: tegra: Ensure timing control debug features are disabled
  memory: tegra: Introduce Tegra30 EMC driver
  memory: tegra: Do not handle error from wait_for_completion_timeout()
  memory: tegra: Increase handshake timeout on Tegra20
  memory: tegra: Print a brief info message about EMC timings
  memory: tegra: Pre-configure debug register on Tegra20
  memory: tegra: Include io.h instead of iopoll.h
  memory: tegra: Adapt for Tegra20 clock driver changes
  memory: tegra: Don't set EMC rate to maximum on probe for Tegra20
  memory: tegra: Add gr2d and gr3d to DRM IOMMU group
  memory: tegra: Set DMA mask based on supported address bits
  soc: at91: Add Atmel SFR SN (Serial Number) support
  memory: atmel-ebi: switch to SPDX license identifiers
  memory: atmel-ebi: move NUM_CS definition inside EBI driver
  soc: mediatek: Refactor bus protection control
  soc: mediatek: Refactor sram control
  ...
</content>
</entry>
<entry>
<title>Merge tag 'char-misc-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc</title>
<updated>2019-11-27T18:53:50Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-11-27T18:53:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8f56e4ebe05c26c30e167519273843476e39e244'/>
<id>urn:sha1:8f56e4ebe05c26c30e167519273843476e39e244</id>
<content type='text'>
Pull char/misc driver updates from Greg KH:
 "Here is the big set of char/misc and other driver patches for 5.5-rc1

  Loads of different things in here, this feels like the catch-all of
  driver subsystems these days. Full details are in the shortlog, but
  nothing major overall, just lots of driver updates and additions.

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'char-misc-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (198 commits)
  char: Fix Kconfig indentation, continued
  habanalabs: add more protection of device during reset
  habanalabs: flush EQ workers in hard reset
  habanalabs: make the reset code more consistent
  habanalabs: expose reset counters via existing INFO IOCTL
  habanalabs: make code more concise
  habanalabs: use defines for F/W files
  habanalabs: remove prints on successful device initialization
  habanalabs: remove unnecessary checks
  habanalabs: invalidate MMU cache only once
  habanalabs: skip VA block list update in reset flow
  habanalabs: optimize MMU unmap
  habanalabs: prevent read/write from/to the device during hard reset
  habanalabs: split MMU properties to PCI/DRAM
  habanalabs: re-factor MMU masks and documentation
  habanalabs: type specific MMU cache invalidation
  habanalabs: re-factor memory module code
  habanalabs: export uapi defines to user-space
  habanalabs: don't print error when queues are full
  habanalabs: increase max jobs number to 512
  ...
</content>
</entry>
</feed>
