linux/drivers/pci/controller/dwc/Makefile, branch master

Merge branch 'pci/controller/dwc-eswin'

2026-04-13T17:50:22Z

- Add DT binding and driver for ESWIN PCIe Root Complex (Senchuan Zhang) * pci/controller/dwc-eswin: PCI: eswin: Add ESWIN PCIe Root Complex driver dt-bindings: PCI: eswin: Add ESWIN PCIe Root Complex # Conflicts: # drivers/pci/controller/dwc/Kconfig # drivers/pci/controller/dwc/Makefile

Merge branch 'pci/controller/dwc-andes-qilai'

2026-04-13T17:50:15Z

- Add Andes QiLai SoC PCIe host driver support (Randolph Lin) * pci/controller/dwc-andes-qilai: PCI: qilai: Add Andes QiLai SoC PCIe host driver support dt-bindings: PCI: Add Andes QiLai PCIe support # Conflicts: # drivers/pci/controller/dwc/Makefile

PCI: eswin: Add ESWIN PCIe Root Complex driver

2026-03-19T21:40:03Z

Add driver for the ESWIN PCIe Root Complex based on the DesignWare PCIe core, IP revision 5.96a. The PCIe Gen.3 Root Complex supports data rate of 8 GT/s and x4 lanes, with INTx and MSI interrupt capability. Signed-off-by: Yu Ning Signed-off-by: Yanghui Ou Signed-off-by: Senchuan Zhang [mani: renamed "EIC7700" to "ESWIN", added maintainers entry, removed async probe] Signed-off-by: Manivannan Sadhasivam [bhelgaas: add driver tag in subject] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20260227111808.1996-1-zhangsenchuan@eswincomputing.com

PCI: qilai: Add Andes QiLai SoC PCIe host driver support

2026-03-05T06:24:48Z

Add driver support for DesignWare based PCIe controller in Andes QiLai SoC. The driver only supports the Root Complex mode. Signed-off-by: Randolph Lin [mani: squashed the MAINTAINERS change] Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260225085504.3757601-4-randolph@andestech.com

PCI: dwc: Remove not-going-to-be-supported code for Baikal SoC

2026-03-02T14:10:35Z

As noticed in the discussion [1] the Baikal SoC and platforms are not going to be finalized, hence remove stale code. Signed-off-by: Andy Shevchenko Signed-off-by: Manivannan Sadhasivam Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/lkml/22b92ddf-6321-41b5-8073-f9c7064d3432@infradead.org/ [1] Link: https://patch.msgid.link/20260220142600.2397070-1-andriy.shevchenko@linux.intel.com

Merge branch 'pci/controller/spacemit-k1'

2025-12-03T20:18:44Z

- Add DT binding and driver for SpacemiT K1 (Alex Elder) * pci/controller/spacemit-k1: PCI: spacemit: Add SpacemiT PCIe host driver dt-bindings: pci: spacemit: Introduce PCIe host controller

Merge branch 'pci/controller/s32g'

2025-12-03T20:18:42Z

- Add NXP S32G host controller DT binding and driver (Vincent Guittot) * pci/controller/s32g: MAINTAINERS: Add NXP S32G PCIe controller driver maintainer PCI: s32g: Add NXP S32G PCIe controller driver (RC) PCI: dwc: Add register and bitfield definitions dt-bindings: PCI: s32g: Add NXP S32G PCIe controller

PCI: s32g: Add NXP S32G PCIe controller driver (RC)

2025-12-02T20:03:11Z

Add initial support of the PCIe controller for the NXP S32G SoC family. Only host mode is supported. Co-developed-by: Ionut Vicovan Signed-off-by: Ionut Vicovan Co-developed-by: Ciprian Marian Costea Signed-off-by: Ciprian Marian Costea Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Signed-off-by: Vincent Guittot [mani: replaced memblock_start_of_DRAM with hardcoded boundary addr] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Frank Li Link: https://patch.msgid.link/20251121164920.2008569-4-vincent.guittot@linaro.org

PCI: spacemit: Add SpacemiT PCIe host driver

2025-11-17T13:29:03Z

Introduce a driver for the PCIe host controller found in the SpacemiT K1 SoC. The hardware is derived from the Synopsys DesignWare PCIe IP. The driver supports up to three PCIe ports operating at PCIe link speed up to 5 GT/s. The first port uses a combo PHY, which may be configured for use for USB3 instead. Signed-off-by: Alex Elder [mani: added FIXME to the comment on disabling ASPM L1] Signed-off-by: Manivannan Sadhasivam Tested-by: Jason Montleon Tested-by: Johannes Erdfelt Tested-by: Aurelien Jarno Link: https://patch.msgid.link/20251113214540.2623070-6-elder@riscstar.com

PCI: keystone: Add support to build as a loadable module

2025-11-13T18:20:46Z

The 'pci-keystone.c' driver is the application/glue/wrapper driver for the Designware PCIe Controllers on TI SoCs. Now that all of the helper APIs that the 'pci-keystone.c' driver depends upon have been exported for use, enable support to build the driver as a loadable module. When building the driver as a module, the functions marked by the '__init' keyword may be invoked after the init memory has been freed by the kernel. This results will result in an exception of the form: Unable to handle kernel paging request at virtual address ... Mem abort info: ... pc : ks_pcie_host_init+0x0/0x540 lr : dw_pcie_host_init+0x170/0x498 ... ks_pcie_host_init+0x0/0x540 (P) ks_pcie_probe+0x728/0x84c platform_probe+0x5c/0x98 really_probe+0xbc/0x29c __driver_probe_device+0x78/0x12c driver_probe_device+0xd8/0x15c To address this, introduce a new function namely 'ks_pcie_init()' to register the 'fault handler' while removing the '__init' keyword from existing functions. Note that hook_fault_code() is defined as '__init' function. Since the init functions should never be called during runtime (after init memory freeing stage), the driver is made as a built-in if CONFIG_ARM (where hook_fault_code() is used) is selected. Signed-off-by: Siddharth Vadapalli [mani: added a note about hook_fault_code()] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20251029080547.1253757-5-s-vadapalli@ti.com