linux/drivers/pci/controller/dwc, branch v5.12

Merge branch 'remotes/lorenzo/pci/misc'

2021-02-24T20:59:25Z

- Remove IRQ handler & data together for altera, brcmstb, dwc (Martin Kaiser) - Fix xgene race in installing chained IRQ handler (Martin Kaiser) - Drop PCIE_RCAR config option (replaced by PCIE_RCAR_HOST) (Lad Prabhakar) - Fix xgene comment about CRS vs CRS SV (Bjorn Helgaas) * remotes/lorenzo/pci/misc: PCI: hv: Fix typo PCI: xgene: Fix CRS SV comment PCI: brcmstb: Remove chained IRQ handler and data in one go PCI: Drop PCIE_RCAR config option PCI: xgene-msi: Fix race in installing chained irq handler PCI: dwc: Remove IRQ handler and data in one go PCI: altera-msi: Remove IRQ handler and data in one go

Merge branch 'pci/qcom'

2021-02-24T20:59:23Z

- Add support for SM8250 PCIe SF TBU clock (Dmitry Baryshkov) - Use PHY_REFCLK_USE_PAD only for qcom ipq8064 (Ansuel Smith) * pci/qcom: PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064 PCI: qcom: Add support for ddrss_sf_tbu clock dt-bindings: PCI: qcom: Document ddrss_sf_tbu clock for sm8250

Merge branch 'pci/layerscape'

2021-02-24T20:59:22Z

- Add Layerscape LX2160A rev2 endpoint mode support (Hou Zhiqiang) - Convert layerscape to builtin_platform_driver() (Michael Walle) * pci/layerscape: PCI: layerscape: Convert to builtin_platform_driver() PCI: layerscape: Add LX2160A rev2 EP mode support dt-bindings: PCI: layerscape: Add LX2160A rev2 compatible strings

PCI: qcom: Use PHY_REFCLK_USE_PAD only for ipq8064

2021-02-24T20:38:49Z

The use of PHY_REFCLK_USE_PAD introduced a regression for apq8064 devices. It was tested that while apq doesn't require the padding, ipq SoC must use it or the kernel hangs on boot. Link: https://lore.kernel.org/r/20201019165555.8269-1-ansuelsmth@gmail.com Fixes: de3c4bf64897 ("PCI: qcom: Add support for tx term offset for rev 2.1.0") Reported-by: Ilia Mirkin Signed-off-by: Ilia Mirkin Signed-off-by: Ansuel Smith Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Acked-by: Stanimir Varbanov Cc: stable@vger.kernel.org # v4.19+

PCI: qcom: Add support for ddrss_sf_tbu clock

2021-02-24T20:38:45Z

On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Link: https://lore.kernel.org/r/20210117013114.441973-3-dmitry.baryshkov@linaro.org Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Signed-off-by: Dmitry Baryshkov Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam Acked-by: Stanimir Varbanov

PCI: al: Remove useless dw_pcie_ops

2021-02-24T17:09:50Z

We have removed the assumption that dw_pcie_ops always exists in the dwc core driver, so we can remove the useless dw_pcie_ops now. Link: https://lore.kernel.org/r/20210128144324.2fa8577c@xhacker.debian Signed-off-by: Jisheng Zhang Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Acked-by: Jonathan Chocron

PCI: dwc: Don't assume the ops in dw_pcie always exist

2021-02-24T17:09:50Z

Some dwc-based device drivers, especially host-only drivers, may work well with the default read_dbi/write_dbi/link_up implementations in pcie-designware.c, so remove the assumption that every driver implements them to simplify those drivers. Link: https://lore.kernel.org/r/20210128144258.10329aa4@xhacker.debian Signed-off-by: Jisheng Zhang Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas

PCI: dwc: Add upper limit address for outbound iATU

2021-02-24T17:09:50Z

The size parameter is unsigned long type which can accept size > 4GB. In that case, the upper limit address must be programmed. Add support to program the upper limit address and set INCREASE_REGION_SIZE in case size > 4GB. Link: https://lore.kernel.org/r/1612250918-19610-1-git-send-email-shradha.t@samsung.com Signed-off-by: Shradha Todi Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Pankaj Dubey Reviewed-by: Rob Herring

PCI: dwc: Change size to u64 for EP outbound iATU

2021-02-24T17:09:50Z

Since outbound iATU permits size to be greater than 4GB for which the support is also available, allow EP function to send u64 size instead of truncating to u32. Link: https://lore.kernel.org/r/1609929900-19082-1-git-send-email-shradha.t@samsung.com Signed-off-by: Shradha Todi Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Pankaj Dubey

PCI: dwc: Drop support for config space in 'ranges'

2021-02-24T17:09:50Z

Since commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code"), the code setting dbi_base when the config space is defined in 'ranges' property instead of 'reg' is dead code as dbi_base is never NULL. Rather than fix this, let's just drop the code. Using ranges has been deprecated since 2014. The only platforms using this were exynos5440, i.MX6 and Spear13xx. Exynos5440 is dead and has been removed. i.MX6 and Spear13xx had PCIe support added just before this was deprecated and were fixed within a kernel release or 2. Link: https://lore.kernel.org/r/20201215194149.86831-1-robh@kernel.org Reported-by: Dan Carpenter Signed-off-by: Rob Herring Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas