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<title>linux/drivers/perf, branch v5.12</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.12</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.12'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2021-03-12T11:30:31Z</updated>
<entry>
<title>perf/arm_dmc620_pmu: Fix error return code in dmc620_pmu_device_probe()</title>
<updated>2021-03-12T11:30:31Z</updated>
<author>
<name>Wei Yongjun</name>
<email>weiyongjun1@huawei.com</email>
</author>
<published>2021-03-12T08:04:21Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c8e3866836528a4ba3b0535834f03768d74f7d8e'/>
<id>urn:sha1:c8e3866836528a4ba3b0535834f03768d74f7d8e</id>
<content type='text'>
Fix to return negative error code -ENOMEM from the error handling
case instead of 0, as done elsewhere in this function.

Fixes: 53c218da220c ("driver/perf: Add PMU driver for the ARM DMC-620 memory controller")
Reported-by: Hulk Robot &lt;hulkci@huawei.com&gt;
Signed-off-by: Wei Yongjun &lt;weiyongjun1@huawei.com&gt;
Link: https://lore.kernel.org/r/20210312080421.277562-1-weiyongjun1@huawei.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu</title>
<updated>2021-02-22T18:31:29Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-02-22T18:31:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d652ea30ba32db12fe8365182fad5ba2e7c22822'/>
<id>urn:sha1:d652ea30ba32db12fe8365182fad5ba2e7c22822</id>
<content type='text'>
Pull iommu updates from Joerg Roedel:

 - ARM SMMU and Mediatek updates from Will Deacon:
     - Support for MT8192 IOMMU from Mediatek
     - Arm v7s io-pgtable extensions for MT8192
     - Removal of TLBI_ON_MAP quirk
     - New Qualcomm compatible strings
     - Allow SVA without hardware broadcast TLB maintenance on SMMUv3
     - Virtualization Host Extension support for SMMUv3 (SVA)
     - Allow SMMUv3 PMU perf driver to be built independently from IOMMU

 - Some tidy-up in IOVA and core code

 - Conversion of the AMD IOMMU code to use the generic IO-page-table
   framework

 - Intel VT-d updates from Lu Baolu:
     - Audit capability consistency among different IOMMUs
     - Add SATC reporting structure support
     - Add iotlb_sync_map callback support

 - SDHI support for Renesas IOMMU driver

 - Misc cleanups and other small improvments

* tag 'iommu-updates-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (94 commits)
  iommu/amd: Fix performance counter initialization
  MAINTAINERS: repair file pattern in MEDIATEK IOMMU DRIVER
  iommu/mediatek: Fix error code in probe()
  iommu/mediatek: Fix unsigned domid comparison with less than zero
  iommu/vt-d: Parse SATC reporting structure
  iommu/vt-d: Add new enum value and structure for SATC
  iommu/vt-d: Add iotlb_sync_map callback
  iommu/vt-d: Move capability check code to cap_audit files
  iommu/vt-d: Audit IOMMU Capabilities and add helper functions
  iommu/vt-d: Fix 'physical' typos
  iommu: Properly pass gfp_t in _iommu_map() to avoid atomic sleeping
  iommu/vt-d: Fix compile error [-Werror=implicit-function-declaration]
  driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3
  MAINTAINERS: Add entry for MediaTek IOMMU
  iommu/mediatek: Add mt8192 support
  iommu/mediatek: Remove unnecessary check in attach_device
  iommu/mediatek: Support master use iova over 32bit
  iommu/mediatek: Add iova reserved function
  iommu/mediatek: Support for multi domains
  iommu/mediatek: Add get_domain_id from dev-&gt;dma_range_map
  ...
</content>
</entry>
<entry>
<title>drivers/perf: Replace spin_lock_irqsave to spin_lock</title>
<updated>2021-02-10T18:50:42Z</updated>
<author>
<name>Qi Liu</name>
<email>liuqi115@huawei.com</email>
</author>
<published>2021-02-09T09:42:22Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=8ee37e0f97ec66b953d202257293670efaab1daa'/>
<id>urn:sha1:8ee37e0f97ec66b953d202257293670efaab1daa</id>
<content type='text'>
There is no need to do spin_lock_irqsave in context of hard IRQ, so
replace them with spin_lock.

Signed-off-by: Qi Liu &lt;liuqi115@huawei.com&gt;
Link: https://lore.kernel.org/r/1612863742-1551-1-git-send-email-liuqi115@huawei.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>drivers/perf: Prevent forced unbinding of ARM_DMC620_PMU drivers</title>
<updated>2021-02-02T18:40:30Z</updated>
<author>
<name>Qi Liu</name>
<email>liuqi115@huawei.com</email>
</author>
<published>2021-02-02T07:58:06Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=20116dd93f4d0b2e84a25ee83e3238586dbb79ec'/>
<id>urn:sha1:20116dd93f4d0b2e84a25ee83e3238586dbb79ec</id>
<content type='text'>
Set "suppress_bind_attrs" to true, so that bind/unbind can be
disabled via sysfs and prevent unbinding ARM_DMC620_PMU drivers
during perf sampling.

Signed-off-by: Qi Liu &lt;liuqi115@huawei.com&gt;
Link: https://lore.kernel.org/r/1612252686-50329-1-git-send-email-liuqi115@huawei.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'arm-smmu-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu</title>
<updated>2021-02-02T12:35:40Z</updated>
<author>
<name>Joerg Roedel</name>
<email>jroedel@suse.de</email>
</author>
<published>2021-02-02T12:35:40Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d1e3306ba83a839462d239ab6dff45ec10f8ce2b'/>
<id>urn:sha1:d1e3306ba83a839462d239ab6dff45ec10f8ce2b</id>
<content type='text'>
Arm SMMU updates for 5.12

- Support for MT8192 IOMMU from Mediatek

- Arm v7s io-pgtable extensions for MT8192

- Removal of TLBI_ON_MAP quirk

- New Qualcomm compatible strings

- Allow SVA without hardware broadcast TLB maintenance on SMMUv3

- Virtualization Host Extension support for SMMUv3 (SVA)

- Allow SMMUv3 PMU (perf) driver to be built independently from IOMMU

- Misc cleanups
</content>
</entry>
<entry>
<title>driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3</title>
<updated>2021-02-01T12:39:40Z</updated>
<author>
<name>John Garry</name>
<email>john.garry@huawei.com</email>
</author>
<published>2021-02-01T10:24:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=34eb9359c111fd17ef8fb1ba671102438a7810c6'/>
<id>urn:sha1:34eb9359c111fd17ef8fb1ba671102438a7810c6</id>
<content type='text'>
The ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3_PMU was added with the idea
that a SMMUv3 PMCG would only exist on a system with an associated SMMUv3.

However it is not the job of Kconfig to make these sorts of decisions (even
if it were true), so remove the dependency.

Signed-off-by: John Garry &lt;john.garry@huawei.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Link: https://lore.kernel.org/r/1612175042-56866-1-git-send-email-john.garry@huawei.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>perf/arm-cmn: Move IRQs when migrating context</title>
<updated>2021-01-28T20:14:45Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2021-01-28T13:12:44Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1c8147ea89c883d1f4e20f1b1d9c879291430102'/>
<id>urn:sha1:1c8147ea89c883d1f4e20f1b1d9c879291430102</id>
<content type='text'>
If we migrate the PMU context to another CPU, we need to remember to
retarget the IRQs as well.

Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver")
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Link: https://lore.kernel.org/r/e080640aea4ed8dfa870b8549dfb31221803eb6b.1611839564.git.robin.murphy@arm.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>perf/arm-cmn: Fix PMU instance naming</title>
<updated>2021-01-28T20:14:45Z</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2021-01-28T13:12:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=79d7c3dca99fa96033695ddf5d495b775a3a137b'/>
<id>urn:sha1:79d7c3dca99fa96033695ddf5d495b775a3a137b</id>
<content type='text'>
Although it's neat to avoid the suffix for the typical case of a
single PMU, it means systems with multiple CMN instances end up with
inconsistent naming. I think it also breaks perf tool's "uncore alias"
logic if the common instance prefix is also the full name of one.

Avoid any surprises by not trying to be clever and simply numbering
every instance, even when it might technically prove redundant.

Fixes: 0ba64770a2f2 ("perf: Add Arm CMN-600 PMU driver")
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Link: https://lore.kernel.org/r/649a2281233f193d59240b13ed91b57337c77b32.1611839564.git.robin.murphy@arm.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>perf: Constify static struct attribute_group</title>
<updated>2021-01-20T17:51:23Z</updated>
<author>
<name>Rikard Falkeborn</name>
<email>rikard.falkeborn@gmail.com</email>
</author>
<published>2021-01-17T21:28:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f0c140481d1b807217cacdcf11d24cfa407a7a53'/>
<id>urn:sha1:f0c140481d1b807217cacdcf11d24cfa407a7a53</id>
<content type='text'>
The only usage is to put their addresses in an array of pointers to
const struct attribute group. Make them const to allow the compiler
to put them in read-only memory.

Signed-off-by: Rikard Falkeborn &lt;rikard.falkeborn@gmail.com&gt;
Link: https://lore.kernel.org/r/20210117212847.21319-5-rikard.falkeborn@gmail.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>perf: hisi: Constify static struct attribute_group</title>
<updated>2021-01-20T17:51:22Z</updated>
<author>
<name>Rikard Falkeborn</name>
<email>rikard.falkeborn@gmail.com</email>
</author>
<published>2021-01-17T21:28:46Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=c2c4d5c051b23dd79ff82d6232347245e11d7c9c'/>
<id>urn:sha1:c2c4d5c051b23dd79ff82d6232347245e11d7c9c</id>
<content type='text'>
The only usage is to put their addresses in an array of pointers to
const struct attribute group. Make them const to allow the compiler
to put them in read-only memory.

Signed-off-by: Rikard Falkeborn &lt;rikard.falkeborn@gmail.com&gt;
Link: https://lore.kernel.org/r/20210117212847.21319-4-rikard.falkeborn@gmail.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
</feed>
