linux/drivers/phy/Makefile, branch v4.11

Revert "phy: Add USB3 PHY support for Broadcom NSP SoC"

2017-03-09T09:59:44Z

This reverts commit d7bc1a7d41bf ("phy: Add USB3 PHY support for Broadcom NSP SoC") as we already have driver for this PHY (shared by NS and NSP). It was added in commit e5666281d9ea ("phy: bcm-ns-usb3: new driver for USB 3.0 PHY on Northstar"). Instead of adding separated driver & duplicating code we should work on improving existing (old) one. Thanks to work done by Broadcom we know there is MDIO bus we weren't aware of & we know register names which makes initialization more clear. This is very valuable info and we should work on using it in existing driver afterwards. Acked-by: Jon Mason Signed-off-by: Rafał Miłecki

Merge tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

2017-02-23T19:53:22Z

Pull PCI updates from Bjorn Helgaas: - add ASPM L1 substate support - enable PCIe Extended Tags when supported - configure PCIe MPS settings on iProc, Versatile, X-Gene, and Xilinx - increase VPD access timeout - add ACS quirks for Intel Union Point, Qualcomm QDF2400 and QDF2432 - use new pci_irq_alloc_vectors() in more drivers - fix MSI affinity memory leak - remove unused MSI interfaces and update documentation - remove unused AER .link_reset() callback - avoid pci_lock / p->pi_lock deadlock seen with perf - serialize sysfs enable/disable num_vfs operations - move DesignWare IP from drivers/pci/host/ to drivers/pci/dwc/ and refactor so we can support both hosts and endpoints - add DT ECAM-like support for HiSilicon Hip06/Hip07 controllers - add Rockchip system power management support - add Thunder-X cn81xx and cn83xx support - add Exynos 5440 PCIe PHY support * tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (93 commits) PCI: dwc: Remove dependency of designware on CONFIG_PCI PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host PCI: dwc: Split pcie-designware.c into host and core files PCI: dwc: designware: Fix style errors in pcie-designware.c PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() PCI: dwc: all: Split struct pcie_port into host-only and core structures PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() PCI: dwc: all: Rename cfg_read/cfg_write to read/write PCI: dwc: all: Use platform_set_drvdata() to save private data PCI: dwc: designware: Move register defines to designware header file PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code PCI: dra7xx: Group PHY API invocations PCI: dra7xx: Enable MSI and legacy interrupts simultaneously PCI: dra7xx: Add support to force RC to work in GEN1 mode PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional() PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory PCI: exynos: Support the PHY generic framework Documentation: binding: Modify the exynos5440 PCIe binding phy: phy-exynos-pcie: Add support for Exynos PCIe PHY Documentation: samsung-phy: Add exynos-pcie-phy binding ...

phy: phy-exynos-pcie: Add support for Exynos PCIe PHY

2017-02-21T13:48:42Z

Add support for Generic PHY framework about Exynos SoCs. Current Exynos PCIe driver doesn't use the PHY framework, which makes it difficult to upstream the other Exynos variants because of different PHY registers. Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe driver. [bhelgaas: depend on "OF && (ARCH_EXYNOS || COMPILE_TEST)", update copyright year, both per Vivek] Signed-off-by: Jaehoon Chung Acked-by: Krzysztof Kozlowski Reviewed-by: Jingoo Han Reviewed-by: Pankaj Dubey Reviewed-by: Vivek Gautam Signed-off-by: Bjorn Helgaas

phy: Add USB3 PHY support for Broadcom NSP SoC

2017-01-27T07:36:53Z

This patch adds support for Broadcom NSP USB3 PHY Signed-off-by: Yendapally Reddy Dhananjaya Reddy Reviewed-by: Florian Fainelli Signed-off-by: Kishon Vijay Abraham I

phy: Add support for Qualcomm's USB HS phy

2017-01-27T07:36:52Z

The high-speed phy on qcom SoCs is controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I Cc: Acked-by: Rob Herring Signed-off-by: Stephen Boyd Signed-off-by: Kishon Vijay Abraham I

phy: Add support for Qualcomm's USB HSIC phy

2017-01-27T07:36:52Z

The HSIC USB controller on qcom SoCs has an integrated all digital phy controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I Acked-by: Rob Herring Cc: Signed-off-by: Stephen Boyd Signed-off-by: Kishon Vijay Abraham I

phy: stih41x-usb: Remove usb phy driver and dt binding

2016-11-18T12:49:15Z

documentation. This phy is only used on STiH415/6 based silicon, and support for these SoC's is being removed from the kernel. Signed-off-by: Peter Griffin Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I

phy: phy-miphy365x: Remove miphy365 driver and dt binding

2016-11-18T12:49:15Z

phy: meson: add USB2 PHY support for Meson8b and GXBB

2016-11-18T12:49:14Z

This is a new driver for the USB PHY found in Meson8b and GXBB SoCs. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Tested-by: Kevin Hilman Signed-off-by: Kishon Vijay Abraham I

phy: Add USB Type-C PHY driver for rk3399

2016-09-10T11:19:01Z

Add a PHY provider driver for the rk3399 SoC Type-c PHY. The USB Type-C PHY is designed to support the USB3 and DP applications. The USB3 operates in SuperSpeed mode and the DP can operate at RBR, HBR and HBR2 data rates. This driver create 2 PHY devices separately for USB3 and DisplyPort, and registers them under the child node. Signed-off-by: Chris Zhong Signed-off-by: Kever Yang Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Signed-off-by: Kishon Vijay Abraham I