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<title>linux/drivers/phy/mediatek, branch v5.1</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.1</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.1'/>
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<updated>2018-12-12T04:31:33Z</updated>
<entry>
<title>phy: core: rework phy_set_mode to accept phy mode and submode</title>
<updated>2018-12-12T04:31:33Z</updated>
<author>
<name>Grygorii Strashko</name>
<email>grygorii.strashko@ti.com</email>
</author>
<published>2018-11-20T01:24:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=79a5a18aa9d1062205cdcfa183d4cd5241d1b8da'/>
<id>urn:sha1:79a5a18aa9d1062205cdcfa183d4cd5241d1b8da</id>
<content type='text'>
Currently the attempt to add support for Ethernet interface mode PHY
(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
duplicate there values from phy_interface_t enum (or introduce more PHY
callbacks) [1]. Both approaches are ineffective and would lead to fast
bloating of enum phy_mode or struct phy_ops in the process of adding more
PHYs for different subsystems which will make them unmaintainable.

As discussed in [1] the solution could be to introduce dual level PHYs mode
configuration - PHY mode and PHY submode. The PHY mode will define generic
PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
specific interface mode. The last is usually already defined in
corresponding subsystem headers (phy_interface_t for Ethernet, enum
usb_device_speed for USB).

This patch is cumulative change which refactors PHY framework code to
support dual level PHYs mode configuration - PHY mode and PHY submode. It
extends .set_mode() callback to support additional parameter "int submode"
and converts all corresponding PHY drivers to support new .set_mode()
callback declaration.
The new extended PHY API
 int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
is introduced to support dual level PHYs mode configuration and existing
phy_set_mode() API is converted to macros, so PHY framework consumers do
not need to be changed (~21 matches).

[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com
Signed-off-by: Grygorii Strashko &lt;grygorii.strashko@ti.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: add property for BC12</title>
<updated>2018-07-10T08:15:08Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2018-06-29T02:20:30Z</published>
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<id>urn:sha1:d4f97f10dac48bf49a199b826c3e8f1c4798bea2</id>
<content type='text'>
Some platforms support BC12 which is disabled by default,
here add a property to enable it if need

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: add properties for eye diagram test</title>
<updated>2018-07-10T08:15:08Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2018-06-29T02:20:29Z</published>
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<id>urn:sha1:8158e917d91cb0be7e6177a7e839fcbb89d63867</id>
<content type='text'>
Add properties for Eye diagram test of HQA which sometimes need
adjust some parameters of u2phy

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: use SPDX license tag</title>
<updated>2018-07-10T08:15:08Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2018-06-29T02:20:27Z</published>
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<id>urn:sha1:3003cfa147e7626d26f6adae819380db600b7fd7</id>
<content type='text'>
Use SPDX-License-Identifier tag instead of the GPL license text

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: mediatek: add XS-PHY driver</title>
<updated>2018-05-20T16:21:35Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2018-05-10T06:10:29Z</published>
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<id>urn:sha1:c1eb8f83845b6ca9e53c41c26a4dff57597d4969</id>
<content type='text'>
Support XS-PHY for MediaTek SoCs with USB3.1 GEN2 controller

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: add configurable parameters for slew rate calibrate</title>
<updated>2018-03-16T08:10:42Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2018-03-12T05:25:39Z</published>
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<id>urn:sha1:8833ebf4f8530834ff8f95f309145f5e2da02999</id>
<content type='text'>
There are two parameters, ref_clk and coefficient, for U2 slew rate
calibrate which may vary on different SoCs, here allow them to be
configurable

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Reviewed-by: Matthias Brugger &lt;matthias.bgg@gmail.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_en</title>
<updated>2018-03-16T08:10:42Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2018-03-12T05:25:38Z</published>
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<id>urn:sha1:4036325609abf29f0dfdffb6e598c56645820f4e</id>
<content type='text'>
The default value of mcu_bus_ck_gate_en is 1, if clear it, will
prevent system to enter deep idle mode, so keep its default value
and without affecting PCIe function.

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: use of_device_get_match_data()</title>
<updated>2017-12-29T07:30:35Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2017-12-28T11:10:36Z</published>
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<id>urn:sha1:e4b227c1ca70ae779c39e5284742555b9e1cdf9f</id>
<content type='text'>
reduce the boilerplate code to get the specific data

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: make shared banks optional for V1 TPHY</title>
<updated>2017-12-29T07:30:35Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2017-12-07T11:53:35Z</published>
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<id>urn:sha1:93a04f4f1607c55452c85c7adaee043321afb3ae</id>
<content type='text'>
V1 TPHY for SATA doesn't have shared banks if it isn't shared
with PCIe or USB, so make it optional.

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: use auto instead of force to bypass utmi signals</title>
<updated>2017-12-29T07:30:35Z</updated>
<author>
<name>Chunfeng Yun</name>
<email>chunfeng.yun@mediatek.com</email>
</author>
<published>2017-12-07T11:53:34Z</published>
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<id>urn:sha1:00c0092c5f62147b7d85f0c6f1cf245a0a1ff3b6</id>
<content type='text'>
When system is running, if usb2 phy is forced to bypass utmi signals,
all PLL will be turned off, and it can't detect device connection
anymore, so replace force mode with auto mode which can bypass utmi
signals automatically if no device attached for normal flow.
But keep the force mode to fix RX sensitivity degradation issue.

Signed-off-by: Chunfeng Yun &lt;chunfeng.yun@mediatek.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
</feed>
