linux/drivers/phy/qualcomm, branch v5.0

phy: ath79-usb: Fix the main reset name to match the DT binding

2019-01-16T12:30:57Z

I submitted this driver several times before it got accepted. The first series hasn't been accepted but the DTS binding did made it. I then made a second series that added generic reset support to the PHY core, this in turn required a change to the DT binding. This second series seemed to have been ignored, so I did a third one without the change to the PHY core and the DT binding update, and this last attempt finally made it. But two months later the DT binding update from the second series has been integrated too. So now the driver doesn't match the binding and the only DTS using it. This patch fix the driver to match the new binding. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I

phy: ath79-usb: Fix the power on error path

2019-01-16T12:30:55Z

In the power on function the error path doesn't return the suspend override to its proper state. It should should deassert this reset line to enable the suspend override. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: Expose provided clocks to DT

2018-12-12T04:32:12Z

Register a simple clock provider for the PHY pipe clock sources so that device tree users can point at these clocks via phandles to the lane nodes. Signed-off-by: Evan Green Reviewed-by: Stephen Boyd Tested-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: Utilize fully-specified DT registers

2018-12-12T04:32:11Z

Utilize the newly fixed up DT bindings to get the tx2 and rx2 register regions for the second lane of dual-lane PHYs. Before this change, the driver was simply using lane one's register region and adding 0x400, which reached well beyond the DT-specified register allocation. This would have been a crash were it not for the page size on ARM64. Fix the driver not to rely on the magic of virtual memory by using the newly specified DT register regions for tx2 and rx2. In order to support existing device trees, this change also contains a fallback mode for when those new register regions don't exist, which reverts to the original behavior of overreaching and prints a complaint. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson Signed-off-by: Kishon Vijay Abraham I

phy: core: rework phy_set_mode to accept phy mode and submode

2018-12-12T04:31:33Z

Currently the attempt to add support for Ethernet interface mode PHY (MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and duplicate there values from phy_interface_t enum (or introduce more PHY callbacks) [1]. Both approaches are ineffective and would lead to fast bloating of enum phy_mode or struct phy_ops in the process of adding more PHYs for different subsystems which will make them unmaintainable. As discussed in [1] the solution could be to introduce dual level PHYs mode configuration - PHY mode and PHY submode. The PHY mode will define generic PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem specific interface mode. The last is usually already defined in corresponding subsystem headers (phy_interface_t for Ethernet, enum usb_device_speed for USB). This patch is cumulative change which refactors PHY framework code to support dual level PHYs mode configuration - PHY mode and PHY submode. It extends .set_mode() callback to support additional parameter "int submode" and converts all corresponding PHY drivers to support new .set_mode() callback declaration. The new extended PHY API int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) is introduced to support dual level PHYs mode configuration and existing phy_set_mode() API is converted to macros, so PHY framework consumers do not need to be changed (~21 matches). [1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com Signed-off-by: Grygorii Strashko Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845

2018-11-21T07:43:58Z

Tune1 register on sdm845 is used to update HSTX_TRIM with fused setting. Enable same by specifying update_tune1_with_efuse flag for sdm845, otherwise driver ends up programming tune2 register. Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845") Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Use HSTX_TRIM fused value as is

2018-11-21T07:43:58Z

Fix HSTX_TRIM tuning logic which instead of using fused value as HSTX_TRIM, incorrectly performs bitwise OR operation with existing default value. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-ufs: Declare 20nm qcom ufs qmp phy as Broken

2018-09-26T07:39:38Z

Fork out separate configs for 14nm and 20nm qcom ufs qmp phys to declare the 20nm phy as broken. Signed-off-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

scsi/ufs: qcom: Remove ufs_qcom_phy_*() calls from host

2018-09-26T07:39:37Z

The host makes direct calls into phy using ufs_qcom_phy_*() APIs. These APIs are only defined for 20nm qcom-ufs-qmp phy which is not being used by any architecture as yet. Future architectures too are not going to use 20nm ufs phy. So remove these ufs_qcom_phy_*() calls from host to let further change declare the 20nm phy as broken. Also remove couple of stale enum defines for ufs phy. Signed-off-by: Vivek Gautam Acked-by: Martin K. Petersen Signed-off-by: Kishon Vijay Abraham I

phy: qcom-ufs: Remove stale methods that handle ref clk

2018-09-26T07:39:36Z

Remove ufs_qcom_phy_enable/(disable)_dev_ref_clk() that are not being used by any code. Signed-off-by: Vivek Gautam Reviewed-by: Bjorn Andersson Signed-off-by: Kishon Vijay Abraham I