linux/drivers/phy/qualcomm, branch v6.3

phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater

2023-02-16T13:10:27Z

For USB 2.0 compliance, eUSB2 needs a repeater. The PHY needs to initialize and reset it. So add repeater support Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230208190200.2966723-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul

phy: qcom: Add QCOM SNPS eUSB2 repeater driver

2023-02-16T13:10:27Z

PM8550B contains a eUSB2 repeater used for making the eUSB2 from SM8550 USB 2.0 compliant. This can be modelled SW-wise as a Phy. So add a new phy driver for it. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230208190200.2966723-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul

Merge tag 'phy-fixes-6.2' into next

2023-02-14T13:55:45Z

Merge fixes tag pulled into mainline by Linus into phy/next due to dependency on amlogic patches

phy: qcom: snps-eusb2: Add missing headers

2023-02-13T16:18:18Z

The driver was missing to include couple of headers explictly which causes build to fail on other archs drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_snps_eusb2_hsphy_write_mask': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:147:15: error: implicit declaration of function 'readl_relaxed' [-Werror=implicit-function-declaration] 147 | reg = readl_relaxed(base + offset); | ^~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:150:9: error: implicit declaration of function 'writel_relaxed' [-Werror=implicit-function-declaration] 150 | writel_relaxed(reg, base + offset); | ^~~~~~~~~~~~~~ drivers/phy/qualcomm/phy-qcom-snps-eusb2.c: In function 'qcom_eusb2_default_parameters': drivers/phy/qualcomm/phy-qcom-snps-eusb2.c:161:42: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration] 161 | FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0)); | ^~~~~~~~~~ Fix this by adding bitfield.h and iopoll.h explictly Fixes: 80090810f5d3 ("phy: qcom: Add QCOM SNPS eUSB2 driver") Reported-by: Stephen Rothwell Reported-by: kernel test robot Signed-off-by: Vinod Koul

phy: qcom-qmp-combo: Add support for SM8550

2023-02-10T17:03:44Z

Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul

phy: qcom-qmp: Add v6 DP register offsets

2023-02-10T17:02:43Z

The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230208183421.2874423-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul

phy: qcom-qmp: pcs-usb: Add v6 register offsets

2023-02-10T17:02:43Z

The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul

phy: qcom: Add QCOM SNPS eUSB2 driver

2023-02-10T17:00:31Z

The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul

phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs

2023-02-10T16:58:01Z

Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org Signed-off-by: Vinod Koul

phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets

2023-02-10T16:58:00Z

The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org Signed-off-by: Vinod Koul