linux/drivers/phy/st, branch v5.12

phy: stm32: rework PLL Lock detection

2021-01-13T15:10:21Z

USBPHYC has a register per phy to control and monitor the debug interface of the HS PHY through a digital debug access. With this register, it is possible to know if PLL Lock input to phy is high. That means the PLL is ready for HS operation. Instead of using an hard-coded delay after PLL enable and PLL disable, use this bit to ensure good operating of the HS PHY. Also use an atomic counter (n_pll_cons) to count the actual number of PLL consumers and get rid of stm32_usbphyc_has_one_phy_active. The boolean active in the usbphyc_phy structure is kept, because we need to know in remove if a phy_exit is required to properly disable the PLL. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210105090525.23164-7-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: ensure phy are no more active when removing the driver

2021-01-13T15:10:21Z

To ensure a good balancing of regulators, and allow PLL disabling when the driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys inactive and disable PLL. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210105090525.23164-6-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: ensure pll is disabled before phys creation

2021-01-13T15:10:21Z

To ensure a good balancing of regulators, force PLL disable either by reset or by clearing the PLLEN bit. If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER instead of polling the PLLEN bit, which will be low at the next probe. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210105090525.23164-5-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: replace regulator_bulk* by multiple regulator_*

2021-01-13T15:10:21Z

Due to async_schedule_domain call in regulator_bulk_enable, scheduling while atomic bug can raise if regulator_bulk_enable is called under atomic context. To avoid this issue, this patch replaces all regulator_bulk* by regulator_ per regulators. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210105090525.23164-4-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation

2021-01-13T15:10:21Z

PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc node and not in phy children nodes. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210105090525.23164-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: defer probe for reset controller

2020-11-16T09:49:03Z

Change stm32-usbphyc driver to defer its probe when the expected reset control has its probe operation deferred. Signed-off-by: Etienne Carriere Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20201110102305.27205-2-amelie.delaunay@st.com Signed-off-by: Vinod Koul

phy: stm32: don't print an error on probe deferral

2020-11-16T09:49:03Z

Change stm32-usbphyc driver to not print an error message when the device probe operation is deferred. Signed-off-by: Etienne Carriere Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20201110130531.7610-1-amelie.delaunay@st.com Signed-off-by: Vinod Koul

phy: phy-stm32-usbphyc: convert to devm_platform_ioremap_resource

2020-11-16T07:17:47Z

Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun Reviewed-by: Amelie Delaunay Link: https://lore.kernel.org/r/1604642930-29019-15-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul

phy: stm32: use NULL instead of zero

2020-07-13T06:45:46Z

devm_clk_get() and devm_reset_control_get() expect a const char *id for the last arg, but a value of zero was provided. This results in below sparse warning: drivers/phy/st/phy-stm32-usbphyc.c:330:42: warning: Using plain integer as NULL pointer drivers/phy/st/phy-stm32-usbphyc.c:343:52: warning: Using plain integer as NULL pointer Instead of zero, use NULL Reviewed-by: Amelie Delaunay Link: https://lore.kernel.org/r/20200708132809.265967-6-vkoul@kernel.org Signed-off-by: Vinod Koul

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman