<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl/Makefile, branch v4.9</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v4.9</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v4.9'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2016-09-07T14:48:22Z</updated>
<entry>
<title>pinctrl: Add core support for Aspeed SoCs</title>
<updated>2016-09-07T14:48:22Z</updated>
<author>
<name>Andrew Jeffery</name>
<email>andrew@aj.id.au</email>
</author>
<published>2016-08-30T07:54:24Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4d3d0e4272d8d660f5f14f5abcf96fb4df1aa94b'/>
<id>urn:sha1:4d3d0e4272d8d660f5f14f5abcf96fb4df1aa94b</id>
<content type='text'>
The Aspeed SoCs typically provide more than 200 pins for GPIO and other
functions. The signal enabled on a pin is determined on a priority
basis, where a given pin can provide a number of different signal types.

In addition to the priority levels, the Aspeed pin controllers describe
the signal active on a pin by compound logical expressions involving
multiple operators, registers and bits. Some difficulty arises as a
pin's function bit masks for each priority level are frequently not the
same (i.e. we cannot just flip a bit to change from a high to low
priority signal), or even in the same register(s). Some configuration
bits affect multiple pins, while in other cases the signals for a bus
must each be enabled individually.

Together, these features give rise to some complexity in the
implementation. A more complete description of the complexities is
provided in the associated header file.

The patch doesn't implement pinctrl/pinmux/pinconf for any particular
Aspeed SoC, rather it adds the framework for defining pinmux
configurations.

Signed-off-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2016-07-29T00:06:51Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2016-07-29T00:06:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=d94ba9e7d8d5c821d0442f13b30b0140c1109c38'/>
<id>urn:sha1:d94ba9e7d8d5c821d0442f13b30b0140c1109c38</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.8 kernel cycle.

  Nothing stands out as especially exiting: new drivers, new subdrivers,
  lots of cleanups and incremental features.

  Business as usual.

  New drivers:

   - New driver for Oxnas pin control and GPIO.  This ARM-based chipset
     is used in a few storage (NAS) type devices.

   - New driver for the MAX77620/MAX20024 pin controller portions.

   - New driver for the Intel Merrifield pin controller.

  New subdrivers:

   - New subdriver for the Qualcomm MDM9615

   - New subdriver for the STM32F746 MCU

   - New subdriver for the Broadcom NSP SoC.

  Cleanups:

   - Demodularization of bool compiled-in drivers.

  Apart from this there is just regular incremental improvements to a
  lot of drivers, especially Uniphier and PFC"

* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
  pinctrl: fix pincontrol definition for marvell
  pinctrl: xway: fix typo
  Revert "pinctrl: amd: make it explicitly non-modular"
  pinctrl: iproc: Add NSP and Stingray GPIO support
  pinctrl: Update iProc GPIO DT bindings
  pinctrl: bcm: add OF dependencies
  pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
  pinctrl: Add STM32F746 MCU support
  pinctrl: intel: Protect set wake flow by spin lock
  pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
  pinctrl: uniphier: add Ethernet pin-mux settings
  sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
  pinctrl: ns2: fix return value check in ns2_pinmux_probe()
  pinctrl: qcom: update DT bindings with ebi2 groups
  pinctrl: qcom: establish proper EBI2 pin groups
  pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
  Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
  includes: dt-bindings: Add STM32F746 pinctrl DT bindings
  pinctrl: sunxi: fix nand0 function name for sun8i
  pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
  ...
</content>
</entry>
<entry>
<title>pinctrl: tegra: Fix build dependency</title>
<updated>2016-06-22T15:58:07Z</updated>
<author>
<name>Axel Lin</name>
<email>axel.lin@ingics.com</email>
</author>
<published>2016-06-04T06:35:56Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=19b5a91764fddcc51b2f8e54a81d4ef231980181'/>
<id>urn:sha1:19b5a91764fddcc51b2f8e54a81d4ef231980181</id>
<content type='text'>
I got below build error:
ERROR: "tegra_xusb_padctl_legacy_probe"
 [drivers/phy/tegra/phy-tegra-xusb.ko] undefined!
with below build configuration:
CONFIG_ARCH_TEGRA=y
CONFIG_PINCTRL_TEGRA_XUSB=y
CONFIG_PHY_TEGRA_XUSB=y

The problem is below line in drivers/pinctrl/Makefile
obj-$(CONFIG_PINCTRL_TEGRA)     += tegra/

So even CONFIG_PINCTRL_TEGRA_XUSB=y is set, kbuild still does not compile
the code in drivers/pinctrl/tegra folder if !CONFIG_PINCTRL_TEGRA.

phy-tegra-xusb.c does not use any symbol from pinctrl-tegra.c,
so build pinctrl-tegra.c only when CONFIG_PINCTRL_TEGRA is set.

Signed-off-by: Axel Lin &lt;axel.lin@ingics.com&gt;
Acked-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Always recurse into bcm folder</title>
<updated>2016-06-13T07:25:31Z</updated>
<author>
<name>Florian Fainelli</name>
<email>f.fainelli@gmail.com</email>
</author>
<published>2016-06-08T21:44:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f886031f65872bb5290a99a8001a68697e2b9faf'/>
<id>urn:sha1:f886031f65872bb5290a99a8001a68697e2b9faf</id>
<content type='text'>
drivers/pinctrl/bcm/Makefile properly builds individual drivers based on
their respective Kconfig symbols. ARCH_BCM is currently a menuconfig
option from arch/arm/mach-bcm/Kconfig, which is fine, but prevents ARM64
platforms which do not have such menuconfig option from building their
pinctrl drivers, so let's get rid of that dependency.

Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Acked-by: Scott Branden &lt;scott.branden@broadcom.com&gt;
Acked-by: Eric Anholt &lt;eric@anholt.net&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: max77620: add pincontrol driver for MAX77620/MAX20024</title>
<updated>2016-05-30T07:41:47Z</updated>
<author>
<name>Laxman Dewangan</name>
<email>ldewangan@nvidia.com</email>
</author>
<published>2016-05-13T05:19:15Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2df723d49cdafb6ea97bf7768879c5197666d300'/>
<id>urn:sha1:2df723d49cdafb6ea97bf7768879c5197666d300</id>
<content type='text'>
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins
which also act as the special function in alternate mode. Also
there is configuration like push-pull, open drain, FPS timing
etc for these pins.

Add pin control driver to configure these parameters through
pin control APIs.

Signed-off-by: Laxman Dewangan &lt;ldewangan@nvidia.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver</title>
<updated>2016-05-30T07:41:45Z</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2016-05-11T07:34:21Z</published>
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<id>urn:sha1:611dac1e48a48baa7b2494f9c07a3f93fc183d11</id>
<content type='text'>
Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family.
This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: mediatek: guard sub-directory with CONFIG_PINCTRL_MTK</title>
<updated>2016-02-13T22:34:19Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-02-10T09:54:32Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4a9e00600b6feeacae02b8ac3428bf98c813c1b2'/>
<id>urn:sha1:4a9e00600b6feeacae02b8ac3428bf98c813c1b2</id>
<content type='text'>
CONFIG_PINCTRL_MTK is more suitable than CONFIG_ARCH_MEDIATEK
to guard the drivers/pinctrl/mediatek/ directory.
(I renamed CONFIG_PINCTRL_MTK_COMMON to CONFIG_PINCTRL_MTK.)

This allows COMPILE_TEST to descend into drivers/pinctrl/mediatek
without CONFIG_ARCH_MEDIATEK define.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: stm32: Fix compile testing selection</title>
<updated>2016-02-09T09:53:35Z</updated>
<author>
<name>Maxime Coquelin</name>
<email>mcoquelin.stm32@gmail.com</email>
</author>
<published>2016-02-08T17:57:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=4afe26845cc291419a2e0af9b4279157a4cd53a7'/>
<id>urn:sha1:4afe26845cc291419a2e0af9b4279157a4cd53a7</id>
<content type='text'>
While selecting the driver for compile testing seemed possible,
the driver was not compiled because the driver directory was only
added if ARCH_STM32 was selected.

This patch now makes the pinctrl Makefile to add stm32 directory if
PINCTRL_STM32 is selected.

Signed-off-by: Maxime Coquelin &lt;mcoquelin.stm32@gmail.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: pinctrl-pic32: Add PIC32 pin control driver</title>
<updated>2016-02-05T22:54:47Z</updated>
<author>
<name>Joshua Henderson</name>
<email>joshua.henderson@microchip.com</email>
</author>
<published>2016-02-01T22:48:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=2ba384e6c3810733e14e183dedc3406f402a686f'/>
<id>urn:sha1:2ba384e6c3810733e14e183dedc3406f402a686f</id>
<content type='text'>
Add a driver for the pin controller present on the Microchip PIC32
including the specific variant PIC32MZDA. This driver provides pinmux
and pinconfig operations as well as GPIO and IRQ chips for the GPIO
banks.

Signed-off-by: Joshua Henderson &lt;joshua.henderson@microchip.com&gt;
Cc: Ralf Baechle &lt;ralf@linux-mips.org&gt;
Cc: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: tegra: move Tegra pinctrl drivers to sub-directory</title>
<updated>2016-02-05T14:16:43Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2016-01-23T15:30:08Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=25cbac7716be6a8d5c57534645ca472d2e4be1fd'/>
<id>urn:sha1:25cbac7716be6a8d5c57534645ca472d2e4be1fd</id>
<content type='text'>
Tegra has several pinctrl drivers.  Now it is reasonable enough to
move them into drivers/pinctrl/tegra/.

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
