<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl/intel, branch v5.4</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.4</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.4'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2019-10-25T09:54:10Z</updated>
<entry>
<title>pinctrl: cherryview: Allocate IRQ chip dynamic</title>
<updated>2019-10-25T09:54:10Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-10-24T13:34:41Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=67d33aecd030226f0a577eb683aaa6853ecf8f91'/>
<id>urn:sha1:67d33aecd030226f0a577eb683aaa6853ecf8f91</id>
<content type='text'>
Keeping the IRQ chip definition static shares it with multiple instances
of the GPIO chip in the system. This is bad and now we get this warning
from GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

This patch is heavily based on the attachment to the bug by Christoph Marz.

BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543
Fixes: 6e08d6bbebeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support")
Depends-on: 83b9dc11312f ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain")
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: cherryview: Fix irq_valid_mask calculation</title>
<updated>2019-10-21T13:57:47Z</updated>
<author>
<name>Hans de Goede</name>
<email>hdegoede@redhat.com</email>
</author>
<published>2019-10-18T09:08:42Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=63bdef6cd6941917c823b9cc9aa0219d19fcb716'/>
<id>urn:sha1:63bdef6cd6941917c823b9cc9aa0219d19fcb716</id>
<content type='text'>
Commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux
GPIO translation") has made the cherryview gpio numbers sparse, to get
a 1:1 mapping between ACPI pin numbers and gpio numbers in Linux.

This has greatly simplified things, but the code setting the
irq_valid_mask was not updated for this, so the valid mask is still in
the old "compressed" numbering with the gaps in the pin numbers skipped,
which is wrong as irq_valid_mask needs to be expressed in gpio numbers.

This results in the following error on devices using pin 24 (0x0018) on
the north GPIO controller as an ACPI event source:

[    0.422452] cherryview-pinctrl INT33FF:01: Failed to translate GPIO to IRQ

This has been reported (by email) to be happening on a Caterpillar CAT T20
tablet and I've reproduced this myself on a Medion Akoya e2215t 2-in-1.

This commit uses the pin number instead of the compressed index into
community-&gt;pins to clear the correct bits in irq_valid_mask for GPIOs
using GPEs for interrupts, fixing these errors and in case of the
Medion Akoya e2215t also fixing the LID switch not working.

Cc: stable@vger.kernel.org
Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Avoid potential glitches if pin is in GPIO mode</title>
<updated>2019-10-21T12:41:19Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-10-14T09:51:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=29c2c6aa32405dfee4a29911a51ba133edcedb0f'/>
<id>urn:sha1:29c2c6aa32405dfee4a29911a51ba133edcedb0f</id>
<content type='text'>
When consumer requests a pin, in order to be on the safest side,
we switch it first to GPIO mode followed by immediate transition
to the input state. Due to posted writes it's luckily to be a single
I/O transaction.

However, if firmware or boot loader already configures the pin
to the GPIO mode, user expects no glitches for the requested pin.
We may check if the pin is pre-configured and leave it as is
till the actual consumer toggles its state to avoid glitches.

Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Depends-on: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip")
Cc: stable@vger.kernel.org
Cc: fei.yang@intel.com
Reported-by: Oliver Barta &lt;oliver.barta@aptiv.com&gt;
Reported-by: Malin Jonsson &lt;malin.jonsson@ericsson.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: cherryview: restore Strago DMI workaround for all versions</title>
<updated>2019-10-01T14:36:40Z</updated>
<author>
<name>Dmitry Torokhov</name>
<email>dmitry.torokhov@gmail.com</email>
</author>
<published>2019-09-24T02:49:58Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=260996c30f4f3a732f45045e3e0efe27017615e4'/>
<id>urn:sha1:260996c30f4f3a732f45045e3e0efe27017615e4</id>
<content type='text'>
This is essentially a revert of:

e3f72b749da2 pinctrl: cherryview: fix Strago DMI workaround
86c5dd6860a6 pinctrl: cherryview: limit Strago DMI workarounds to version 1.0

because even with 1.1 versions of BIOS there are some pins that are
configured as interrupts but not claimed by any driver, and they
sometimes fire up and result in interrupt storms that cause touchpad
stop functioning and other issues.

Given that we are unlikely to qualify another firmware version for a
while it is better to keep the workaround active on all Strago boards.

Reported-by: Alex Levin &lt;levinale@chromium.org&gt;
Fixes: 86c5dd6860a6 ("pinctrl: cherryview: limit Strago DMI workarounds to version 1.0")
Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Torokhov &lt;dmitry.torokhov@gmail.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Tested-by: Alex Levin &lt;levinale@chromium.org&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Allocate IRQ chip dynamic</title>
<updated>2019-10-01T14:36:07Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-09-16T14:47:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=57ff2df1b952c7934d7b0e1d3a2ec403ec76edec'/>
<id>urn:sha1:57ff2df1b952c7934d7b0e1d3a2ec403ec76edec</id>
<content type='text'>
Keeping the IRQ chip definition static shares it with multiple instances of
the GPIO chip in the system. This is bad and now we get this warning from
GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

Fixes: ee1a6ca43dba ("pinctrl: intel: Add Intel Broxton pin controller support")
Depends-on: 5ff56b015e85 ("pinctrl: intel: Disable GPIO pin interrupts in suspend")
Reported-by: Federico Ricchiuto &lt;fed.ricchiuto@gmail.com&gt;
Suggested-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2019-09-19T21:19:33Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-09-19T21:19:33Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3c2edc36a77420d8be05d656019dbc8c31535992'/>
<id>urn:sha1:3c2edc36a77420d8be05d656019dbc8c31535992</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.4 kernel cycle:

  Core changes:

   - Fix errors in example code in the documentation.

  New drivers:

   - Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
     Ingenic driver.

   - Support Cirrus Logic Madera CS47L92 and CS47L15.

   - Support Allwinner Sunxi V3S.

   - Support Aspeed 2600 BMC.

   - Support Qualcomm SC7180.

   - Support Marvell MVEBU CS115.

  Driver improvements:

   - Clean up a few drivers to use the devm_platform_ioremap_resource()
     helper.

   - Pass the irqchip when registering the gpio_chip in some pin
     controllers that are also GPIO controllers.

   - Support suspend/resume in the Tegra driver.

   - Support pull-up on the Broadcom BCM2711.

   - The Intel driver can now request locked pads.

   - Fix the UFS reset pin in the Qualcomm SDM845 driver"

* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
  pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
  pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
  pinctrl: bcm: remove redundant assignment to pointer log
  pinctrl: iproc: Add 'get_direction' support
  pinctrl: iproc-gpio: Handle interrupts for multiple instances
  pinctrl: iproc-gpio: Fix incorrect pinconf configurations
  pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
  pinctrl: qcom: sdm845: Fix UFS_RESET pin
  pinctrl: mvebu: add additional variant for standalone CP115
  pinctrl: mvebu: Add CP110 missing pin functionality
  dt-bindings: cp110: document the new CP115 pinctrl compatible
  pinctrl: bcm2835: Pass irqchip when adding gpiochip
  pinctrl: meson: meson: Add of_node_put() before return
  pinctrl/gpio: Take MUX usage into account
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
  pinctrl: amd: disable spurious-firing GPIO IRQs
  pinctrl: rza2: Include the appropriate headers
  pinctrl: rza2: Drop driver use of consumer flags
  ...
</content>
</entry>
<entry>
<title>gpio: Initialize the irqchip valid_mask with a callback</title>
<updated>2019-09-11T00:09:37Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-09-04T14:01:04Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=5fbe5b5883f847363ff1b7280e8b1d2980526b8e'/>
<id>urn:sha1:5fbe5b5883f847363ff1b7280e8b1d2980526b8e</id>
<content type='text'>
After changing the valid_mask for the struct gpio_chip
to detect the need and presence of a valid mask with the
presence of a .init_valid_mask() callback to fill it in,
we augment the gpio_irq_chip to use the same logic.

Switch all driver using the gpio_irq_chio valid_mask
over to this new method.

This makes sure the valid_mask for the gpio_irq_chip gets
filled in when we add the gpio_chip, which makes it a
little easier to switch over drivers using the old
way of setting up gpio_irq_chip over to the new method
of passing the gpio_irq_chip along with the gpio_chip.
(See drivers/gpio/TODO for details.)

Cc: Joel Stanley &lt;joel@jms.id.au&gt;
Cc: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Tested-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed-by: Andrew Jeffery &lt;andrew@aj.id.au&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Link: https://lore.kernel.org/r/20190904140104.32426-1-linus.walleij@linaro.org
</content>
</entry>
<entry>
<title>pinctrl: intel: mark intel_pin_to_gpio __maybe_unused</title>
<updated>2019-09-09T10:11:42Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2019-09-06T18:51:59Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=55dac43747be98516a337285428806d177afaa3a'/>
<id>urn:sha1:55dac43747be98516a337285428806d177afaa3a</id>
<content type='text'>
The intel_pin_to_gpio() function is only called by the
PM support functions and causes a warning when those are disabled:

drivers/pinctrl/intel/pinctrl-intel.c:841:12: error: unused function 'intel_pin_to_gpio' [-Werror,-Wunused-function]

Mark it __maybe_unused to suppress the warning.

Suggested-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Reviewed-by: Chris Chiu &lt;chiu@endlessm.com&gt;
Acked-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: remap the pin number to gpio offset for irq enabled pin</title>
<updated>2019-08-19T09:41:44Z</updated>
<author>
<name>Chris Chiu</name>
<email>chiu@endlessm.com</email>
</author>
<published>2019-08-16T09:38:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6cb0880f08229360c6c57416de075aa96930be78'/>
<id>urn:sha1:6cb0880f08229360c6c57416de075aa96930be78</id>
<content type='text'>
On Asus X571GT, GPIO 297 is configured as an interrupt and serves
for the touchpad. The touchpad will report input events much less
than expected after S3 suspend/resume, which results in extremely
slow cursor movement. However, the number of interrupts observed
from /proc/interrupts increases much more than expected even no
touching touchpad.

This is due to the value of PADCFG0 of PIN 225 for the interrupt
has been changed from 0x80800102 to 0x80100102. The GPIROUTIOXAPIC
is toggled on which results in the spurious interrupts. The PADCFG0
of PIN 225 is expected to be saved during suspend, but the 297 is
saved instead because the gpiochip_line_is_irq() expect the GPIO
offset but what's really passed to it is PIN number. In this case,
the /sys/kernel/debug/pinctrl/INT3450:00/gpio-ranges shows

288: INT3450:00 GPIOS [436 - 459] PINS [216 - 239]

So gpiochip_line_is_irq() returns true for GPIO offset 297, the
suspend routine spuriously saves the content for PIN 297 which
we expect to save for PIN 225.

This commit maps the PIN number to GPIO offset first in the
intel_pinctrl_should_save() to make sure the values for the
specific PINs can be correctly saved and then restored.

Fixes: c538b9436751 ("pinctrl: intel: Only restore pins that are used by the driver")
Signed-off-by: Chris Chiu &lt;chiu@endlessm.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Allow to request locked pads</title>
<updated>2019-08-18T17:57:50Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-08-12T16:14:01Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=1bd231538c21d1cd691e71cbeeb4100fabc58068'/>
<id>urn:sha1:1bd231538c21d1cd691e71cbeeb4100fabc58068</id>
<content type='text'>
Some firmwares would like to protect pads from being modified by OS
and at the same time provide them to OS as a resource. So, the driver
in such circumstances may request pad and may not change its state.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
</feed>
