<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl/intel, branch v5.6</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=v5.6</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=v5.6'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2020-01-16T11:30:40Z</updated>
<entry>
<title>pinctrl: tigerlake: Tiger Lake uses _HID enumeration</title>
<updated>2020-01-16T11:30:40Z</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2020-01-16T11:09:02Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=cd0a32371db73d0b50536a7ca4f036abddff0d1d'/>
<id>urn:sha1:cd0a32371db73d0b50536a7ca4f036abddff0d1d</id>
<content type='text'>
Turns out that Tiger Lake GPIO will be enumerated using _HID method where
there is only a single ACPI device and multiple BARs so rework the driver
to support that scheme instead.

Fixes: c9ccf71fc807 ("pinctrl: intel: Add Intel Tiger Lake pin controller support")
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID</title>
<updated>2020-01-16T11:30:19Z</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2020-01-16T11:09:51Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=899b7e3374b253888b048dd06338e043e4b7637c'/>
<id>urn:sha1:899b7e3374b253888b048dd06338e043e4b7637c</id>
<content type='text'>
Intel Coffee Lake-S PCH has the same GPIO hardware than Sunrisepoint-H
PCH but the ACPI ID is different. Add this new ACPI ID to the list of
supported devices.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Pass irqchip when adding gpiochip</title>
<updated>2020-01-09T11:12:20Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-01-09T07:53:29Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=af0c5330916a1ffd6cc0ffd6bea50688d99bf444'/>
<id>urn:sha1:af0c5330916a1ffd6cc0ffd6bea50688d99bf444</id>
<content type='text'>
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward conversion.

Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add GPIO &lt;-&gt; pin mapping ranges via callback</title>
<updated>2020-01-09T11:12:20Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-01-09T07:53:28Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=6d416b9bb577cc3013301cfccb0d938567af489d'/>
<id>urn:sha1:6d416b9bb577cc3013301cfccb0d938567af489d</id>
<content type='text'>
When IRQ chip is instantiated via GPIO library flow, the few functions,
in particular the ACPI event registration mechanism, on some of ACPI based
platforms expect that the pin ranges are initialized to that point.

Add GPIO &lt;-&gt; pin mapping ranges via callback in the GPIO library flow.

Cc: Hans de Goede &lt;hdegoede@redhat.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output</title>
<updated>2020-01-09T11:12:20Z</updated>
<author>
<name>Hans de Goede</name>
<email>hdegoede@redhat.com</email>
</author>
<published>2020-01-01T14:52:43Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e2b74419e5cc7cfc58f3e785849f73f8fa0af5b3'/>
<id>urn:sha1:e2b74419e5cc7cfc58f3e785849f73f8fa0af5b3</id>
<content type='text'>
Suspending Goodix touchscreens requires changing the interrupt pin to
output before sending them a power-down command. Followed by wiggling
the interrupt pin to wake the device up, after which it is put back
in input mode.

On Cherry Trail device the interrupt pin is listed as a GpioInt ACPI
resource so we can do this without problems as long as we release the
IRQ before changing the pin to output mode.

On Bay Trail devices with a Goodix touchscreen direct-irq mode is used
in combination with listing the pin as a normal GpioIo resource. This
works fine, but this triggers the WARN in byt_gpio_set_direction-s output
path because direct-irq support is enabled on the pin.

This commit replaces the WARN call with a dev_info_once call, fixing a
bunch of WARN splats in dmesg on each suspend/resume cycle.

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins</title>
<updated>2020-01-09T11:11:17Z</updated>
<author>
<name>Hans de Goede</name>
<email>hdegoede@redhat.com</email>
</author>
<published>2019-12-27T23:04:47Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a23680594da7a9e2696dbcf4f023e9273e2fa40b'/>
<id>urn:sha1:a23680594da7a9e2696dbcf4f023e9273e2fa40b</id>
<content type='text'>
Suspending Goodix touchscreens requires changing the interrupt pin to
output before sending them a power-down command. Followed by wiggling
the interrupt pin to wake the device up, after which it is put back
in input mode.

On Bay Trail devices with a Goodix touchscreen direct-irq mode is used
in combination with listing the pin as a normal GpioIo resource.

This works fine, until the goodix driver gets rmmod-ed and then insmod-ed
again. In this case byt_gpio_disable_free() calls
byt_gpio_clear_triggering() which clears the IRQ flags and after that the
(direct) IRQ no longer triggers.

This commit fixes this by adding a check for the BYT_DIRECT_IRQ_EN flag
to byt_gpio_clear_triggering().

Note that byt_gpio_clear_triggering() only gets called from
byt_gpio_disable_free() for direct-irq enabled pins, as these are excluded
from the irq_valid mask by byt_init_irq_valid_mask().

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: sunrisepoint: Add missing Interrupt Status register offset</title>
<updated>2020-01-08T16:35:24Z</updated>
<author>
<name>Boyan Ding</name>
<email>boyan.j.ding@gmail.com</email>
</author>
<published>2020-01-01T20:41:20Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=f0682757230bdfc58118125dc81d805a427766b8'/>
<id>urn:sha1:f0682757230bdfc58118125dc81d805a427766b8</id>
<content type='text'>
Commit 179e5a6114cc ("pinctrl: intel: Remove default Interrupt Status
offset") removes default interrupt status offset of GPIO controllers,
with previous commits explicitly providing the previously default
offsets. However, the is_offset value in SPTH_COMMUNITY is missing,
preventing related irq from being properly detected and handled.

Fixes: f702e0b93cdb ("pinctrl: sunrisepoint: Provide Interrupt Status register offset")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=205745
Cc: stable@vger.kernel.org
Signed-off-by: Boyan Ding &lt;boyan.j.ding@gmail.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: lynxpoint: Update summary in the driver</title>
<updated>2019-12-13T14:48:49Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-11-25T15:45:45Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3a67fe38e76a590d2c8ce4731cd64fbd477e5f79'/>
<id>urn:sha1:3a67fe38e76a590d2c8ce4731cd64fbd477e5f79</id>
<content type='text'>
Reflect in the driver that it is now a pin control one.

While here, update copyright years and authors.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: lynxpoint: Switch to pin control API</title>
<updated>2019-12-13T14:48:49Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-11-25T17:30:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=64e14e90646cafa9940cead9f7ba336c55671bf9'/>
<id>urn:sha1:64e14e90646cafa9940cead9f7ba336c55671bf9</id>
<content type='text'>
When all preparations are done, we may switch to pin control API.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: lynxpoint: Add GPIO &lt;-&gt; pin mapping ranges via callback</title>
<updated>2019-12-13T14:48:48Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-11-04T17:07:30Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=3683509c3910cb377913dcd430447ad48f676b31'/>
<id>urn:sha1:3683509c3910cb377913dcd430447ad48f676b31</id>
<content type='text'>
When IRQ chip is instantiated via GPIO library flow, the few functions,
in particular the ACPI event registration mechanism, on some of ACPI based
platforms expect that the pin ranges are initialized to that point.

Add GPIO &lt;-&gt; pin mapping ranges via callback in the GPIO library flow.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
</feed>
