linux/drivers/pinctrl/intel, branch v5.7

pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

2020-04-17T11:37:40Z

According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e. cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler") Fixes: 0bd50d719b00 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers") Signed-off-by: Grace Kao Reported-by: Brian Norris Reviewed-by: Brian Norris Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: baytrail: Enable pin configuration setting for GPIO chip

2020-04-13T10:14:35Z

It appears that pin configuration for GPIO chip hasn't been enabled yet due to absence of ->set_config() callback. Enable it here for Intel Baytrail. Fixes: c501d0b149de ("pinctrl: baytrail: Add pin control operations") Depends-on: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H

2020-04-13T10:14:35Z

It appears that SPT-H variant has different offset for PAD locking registers. Fix it here. Fixes: 551fa5801ef1 ("pinctrl: intel: sunrisepoint: Add Intel Sunrisepoint-H support") Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg

pinctrl: tigerlake: Tiger Lake uses _HID enumeration

2020-01-16T11:30:40Z

Turns out that Tiger Lake GPIO will be enumerated using _HID method where there is only a single ACPI device and multiple BARs so rework the driver to support that scheme instead. Fixes: c9ccf71fc807 ("pinctrl: intel: Add Intel Tiger Lake pin controller support") Signed-off-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID

2020-01-16T11:30:19Z

Intel Coffee Lake-S PCH has the same GPIO hardware than Sunrisepoint-H PCH but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Signed-off-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: intel: Pass irqchip when adding gpiochip

2020-01-09T11:12:20Z

We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Hans de Goede Signed-off-by: Linus Walleij Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: intel: Add GPIO <-> pin mapping ranges via callback

2020-01-09T11:12:20Z

When IRQ chip is instantiated via GPIO library flow, the few functions, in particular the ACPI event registration mechanism, on some of ACPI based platforms expect that the pin ranges are initialized to that point. Add GPIO <-> pin mapping ranges via callback in the GPIO library flow. Cc: Hans de Goede Signed-off-by: Linus Walleij Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output

2020-01-09T11:12:20Z

Suspending Goodix touchscreens requires changing the interrupt pin to output before sending them a power-down command. Followed by wiggling the interrupt pin to wake the device up, after which it is put back in input mode. On Cherry Trail device the interrupt pin is listed as a GpioInt ACPI resource so we can do this without problems as long as we release the IRQ before changing the pin to output mode. On Bay Trail devices with a Goodix touchscreen direct-irq mode is used in combination with listing the pin as a normal GpioIo resource. This works fine, but this triggers the WARN in byt_gpio_set_direction-s output path because direct-irq support is enabled on the pin. This commit replaces the WARN call with a dev_info_once call, fixing a bunch of WARN splats in dmesg on each suspend/resume cycle. Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko

pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins

2020-01-09T11:11:17Z

Suspending Goodix touchscreens requires changing the interrupt pin to output before sending them a power-down command. Followed by wiggling the interrupt pin to wake the device up, after which it is put back in input mode. On Bay Trail devices with a Goodix touchscreen direct-irq mode is used in combination with listing the pin as a normal GpioIo resource. This works fine, until the goodix driver gets rmmod-ed and then insmod-ed again. In this case byt_gpio_disable_free() calls byt_gpio_clear_triggering() which clears the IRQ flags and after that the (direct) IRQ no longer triggers. This commit fixes this by adding a check for the BYT_DIRECT_IRQ_EN flag to byt_gpio_clear_triggering(). Note that byt_gpio_clear_triggering() only gets called from byt_gpio_disable_free() for direct-irq enabled pins, as these are excluded from the irq_valid mask by byt_init_irq_valid_mask(). Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Reviewed-by: Linus Walleij Signed-off-by: Andy Shevchenko

pinctrl: sunrisepoint: Add missing Interrupt Status register offset

2020-01-08T16:35:24Z

Commit 179e5a6114cc ("pinctrl: intel: Remove default Interrupt Status offset") removes default interrupt status offset of GPIO controllers, with previous commits explicitly providing the previously default offsets. However, the is_offset value in SPTH_COMMUNITY is missing, preventing related irq from being properly detected and handled. Fixes: f702e0b93cdb ("pinctrl: sunrisepoint: Provide Interrupt Status register offset") Link: https://bugzilla.kernel.org/show_bug.cgi?id=205745 Cc: stable@vger.kernel.org Signed-off-by: Boyan Ding Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko