<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux/drivers/pinctrl/qcom, branch master</title>
<subtitle>Mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
</subtitle>
<id>https://git.shady.money/linux/atom?h=master</id>
<link rel='self' href='https://git.shady.money/linux/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/'/>
<updated>2026-04-18T23:59:09Z</updated>
<entry>
<title>Merge tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2026-04-18T23:59:09Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-04-18T23:59:09Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=faeab166167f5787719eb8683661fd41a3bb1514'/>
<id>urn:sha1:faeab166167f5787719eb8683661fd41a3bb1514</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "Core changes:

   - Perform basic checks on pin config properties so as not to allow
     directly contradictory settings such as setting a pin to more than
     one bias or drive mode

   - Handle input-threshold-voltage-microvolt property

   - Introduce pinctrl_gpio_get_config() handling in the core for SCMI
     GPIO using pin control

  New drivers:

   - GPIO-by-pin control driver (also appearing in the GPIO pull
     request) fulfilling a promise on a comment from Grant Likely many
     years ago: "can't GPIO just be a front-end for pin control?" it
     turns out it can, if and only if you design something new from
     scratch, such as SCMI

   - Broadcom BCM7038 as a pinctrl-single delegate

   - Mobileye EyeQ6Lplus OLB pin controller

   - Qualcomm Eliza and Hawi families TLMM pin controllers

   - Qualcomm SDM670 and Milos family LPASS LPI pin controllers

   - Qualcomm IPQ5210 pin controller

   - Realtek RTD1625 pin controller support

   - Rockchip RV1103B pin controller support

   - Texas Instruments AM62L as a pinctrl-single delegate

  Improvements:

   - Set config implementation for the Spacemit K1 pin controller"

* tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (84 commits)
  pinctrl: qcom: Add Hawi pinctrl driver
  dt-bindings: pinctrl: qcom: Describe Hawi TLMM block
  dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema
  pinctrl: single: Add bcm7038-padconf compatible matching
  dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf
  dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible
  pinctrl: qcom: sdm670-lpass-lpi: label variables as static
  pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description
  pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description
  pinctrl: qcom: add sdm670 lpi tlmm
  dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl
  dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property
  pinctrl: qcom: Introduce IPQ5210 TLMM driver
  dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
  pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs
  pinctrl: qcom: eliza: Fix interrupt target bit
  pinctrl: core: Don't use "proxy" headers
  pinctrl: amd: Support new ACPI ID AMDI0033
  pinctrl: renesas: rzg2l: Drop superfluous blank line
  pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers
  ...
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add Hawi pinctrl driver</title>
<updated>2026-04-09T08:52:34Z</updated>
<author>
<name>Mukesh Ojha</name>
<email>mukesh.ojha@oss.qualcomm.com</email>
</author>
<published>2026-04-08T14:15:48Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=90700e10d2ad61c13a5117cfa5e08d9f2e497dcc'/>
<id>urn:sha1:90700e10d2ad61c13a5117cfa5e08d9f2e497dcc</id>
<content type='text'>
Add pinctrl driver for TLMM block found in the Hawi SoC.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Signed-off-by: Mukesh Ojha &lt;mukesh.ojha@oss.qualcomm.com&gt;
Reviewed-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: sdm670-lpass-lpi: label variables as static</title>
<updated>2026-04-09T07:20:56Z</updated>
<author>
<name>Richard Acayan</name>
<email>mailingradian@gmail.com</email>
</author>
<published>2026-04-08T22:30:38Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=7fe21f1ef74f2f4b95896789db656c84b22f01c1'/>
<id>urn:sha1:7fe21f1ef74f2f4b95896789db656c84b22f01c1</id>
<content type='text'>
These variables are local to the driver and have no need to be exported
to the global namespace. Label them as static to fix compiler warnings.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Closes: https://lore.kernel.org/oe-kbuild-all/202604080950.Mvm8aN0a-lkp@intel.com/
Fixes: 9826035a75da ("pinctrl: qcom: add sdm670 lpi tlmm")
Signed-off-by: Richard Acayan &lt;mailingradian@gmail.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: add sdm670 lpi tlmm</title>
<updated>2026-04-07T07:01:55Z</updated>
<author>
<name>Richard Acayan</name>
<email>mailingradian@gmail.com</email>
</author>
<published>2026-03-31T20:06:57Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=9826035a75da609ac2424c97915d6fe5b836ee65'/>
<id>urn:sha1:9826035a75da609ac2424c97915d6fe5b836ee65</id>
<content type='text'>
The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.

Signed-off-by: Richard Acayan &lt;mailingradian@gmail.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Introduce IPQ5210 TLMM driver</title>
<updated>2026-03-30T08:47:39Z</updated>
<author>
<name>Kathiravan Thirumoorthy</name>
<email>kathiravan.thirumoorthy@oss.qualcomm.com</email>
</author>
<published>2026-03-30T04:51:05Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=a549fe22376f5c312d9f61965184265425c8fd28'/>
<id>urn:sha1:a549fe22376f5c312d9f61965184265425c8fd28</id>
<content type='text'>
Qualcomm's IPQ5210 SoC comes with a TLMM block, like all other platforms,
so add a driver for it.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
Signed-off-by: Kathiravan Thirumoorthy &lt;kathiravan.thirumoorthy@oss.qualcomm.com&gt;
[linusw@kernel.org: Dropped intr_target_reg]
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs</title>
<updated>2026-03-30T08:29:59Z</updated>
<author>
<name>Mukesh Ojha</name>
<email>mukesh.ojha@oss.qualcomm.com</email>
</author>
<published>2026-03-27T17:12:40Z</published>
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<id>urn:sha1:0720208b37ae4f1193dc7103ee269b180a8f8943</id>
<content type='text'>
On all Qualcomm TLMM generations from APQ8084 onwards, the interrupt
target routing bits are located in the same register as the interrupt
configuration bits (intr_cfg_reg). Only five older SoCs — APQ8064,
IPQ8064, MDM9615, MSM8660 and MSM8960 — have a genuinely separate
interrupt target routing register at a different offset (0x400 + 0x4 * id).

Replace MSM_ACCESSOR(intr_target) with a custom accessor that falls back
to intr_cfg_reg when intr_target_reg is zero. Apply the same fallback in
the SCM path. Drop the now-redundant .intr_target_reg initializer from
all SoC drivers where it duplicated intr_cfg_reg, keeping it only in
the five drivers where it genuinely differs.

Signed-off-by: Mukesh Ojha &lt;mukesh.ojha@oss.qualcomm.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: eliza: Fix interrupt target bit</title>
<updated>2026-03-30T08:29:54Z</updated>
<author>
<name>Mukesh Ojha</name>
<email>mukesh.ojha@oss.qualcomm.com</email>
</author>
<published>2026-03-27T17:12:39Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=fe8933c5b3e2e5294f82da546792268e5687391e'/>
<id>urn:sha1:fe8933c5b3e2e5294f82da546792268e5687391e</id>
<content type='text'>
The intr_target_bit for Eliza was incorrectly set to 5, which is the
value used by older Qualcomm SoCs (e.g. SM8250, MSM8996, X1E80100).
Newer SoCs such as SM8650, SM8750, Milos, and Kaanapali all use
bit 8 for the interrupt target field in the TLMM interrupt configuration
register.

Eliza belongs to the newer generation and should use bit 8 to correctly
route interrupts to the KPSS (Applications Processor). Using the wrong
bit position means the interrupt target routing is silently misconfigured,
which can result in GPIO interrupts not being delivered to the expected
processor.

Fix this by aligning Eliza with the correct value used by its peer SoCs.

Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver")
Signed-off-by: Mukesh Ojha &lt;mukesh.ojha@oss.qualcomm.com&gt;
Reviewed-by: Abel Vesa &lt;abel.vesa@oss.qualcomm.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add Milos LPASS LPI TLMM</title>
<updated>2026-03-10T11:27:17Z</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2026-03-06T14:22:16Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=ca0395d9ef294a4340104107177de23e04de2344'/>
<id>urn:sha1:ca0395d9ef294a4340104107177de23e04de2344</id>
<content type='text'>
Add a driver for the pin controller in the Low Power Audio SubSystem
(LPASS) on the Milos SoC.

Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: spmi-gpio: implement .get_direction()</title>
<updated>2026-03-10T09:21:52Z</updated>
<author>
<name>Neil Armstrong</name>
<email>neil.armstrong@linaro.org</email>
</author>
<published>2026-03-04T17:41:08Z</published>
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<id>urn:sha1:263447532463cf4444a3595e835b99a4e90952fa</id>
<content type='text'>
GPIO controller driver should typically implement the .get_direction()
callback as GPIOLIB internals may try to use it to determine the state
of a pin. Since introduction of shared proxy, it prints a warning splat
when using a shared spmi gpio.

The implementation is not easy because the controller supports enabling
the input and output logic at the same time, so we aligns on the
behaviour of the .get() operation and return -EINVAL in other
situations.

Fixes: eadff3024472 ("pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver")
Fixes: d7b5f5cc5eb4 ("pinctrl: qcom: spmi-gpio: Add support for GPIO LV/MV subtype")
Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Bartosz Golaszewski &lt;bartosz.golaszewski@oss.qualcomm.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: sdm660-lpass-lpi: Make groups and functions variables static</title>
<updated>2026-02-24T09:51:30Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@oss.qualcomm.com</email>
</author>
<published>2026-02-16T08:25:50Z</published>
<link rel='alternate' type='text/html' href='https://git.shady.money/linux/commit/?id=e9e268ea9df102abef34d7afba59ef4d5868d5d7'/>
<id>urn:sha1:e9e268ea9df102abef34d7afba59ef4d5868d5d7</id>
<content type='text'>
File-scope 'sdm660_lpi_pinctrl_groups' and
'sdm660_lpi_pinctrl_functions' are not used outside of this unit, so
make them static to silence sparse warnings:

  pinctrl-sdm660-lpass-lpi.c:79:27: warning: symbol 'sdm660_lpi_pinctrl_groups' was not declared. Should it be static?
  pinctrl-sdm660-lpass-lpi.c:116:27: warning: symbol 'sdm660_lpi_pinctrl_functions' was not declared. Should it be static?

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Signed-off-by: Linus Walleij &lt;linusw@kernel.org&gt;
</content>
</entry>
</feed>
